on Low Power Design Impact on Test and Reliability (LPonTR)
LPonTR workshop aims to bring together design, reliability and test
engineers and researchers to discuss the impact of advanced low-power /
low voltage design
methodologies of nanometer silicon systems on test and reliability.
Power and thermal issues, leakage, process variations, enhanced
susceptibility to environmental and operation-induced disturbances are
physical constraints that drive the need to the development of
low-power, process-tolerant design techniques. However, these
techniques generate a new set of test and reliability challenges,
questing for an innovative set of methodologies and tools.
LPonTR workshop will be held at theGrand Hotel Majestic,