13th IEEE European Test Symposium
Verbania, ITALY, May 25-29, 2008

 
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May 26th, 2008 technical program
May 27th, 2008 program at-a-glance
May 28th, 2008
   
*shaded papers are informal 
   
May 26th, 2008
8:30-10:30 Session 1: Plenary Opening
Sala Toscanini Moderator: Zebo PENG (Linköping University - Sweden)
 
8:30-9:10    Opening ceremony
 
  » Welcome Address
    Matteo SONZA REORDA (Politecnico di Torino - Italy)
ETS’08 General Chair
 
»  Technical Program Introduction
Patrick GIRARD (LIRMM - France)
ETS’08 Program Chair
 
» Presentation of ETS'07 Best Paper Award
Zebo PENG (Linköping University - Sweden)
ETS’07 Program Chair
 
» TTTC Award Ceremony
Yervant Zorian (Virage Logic - USA)
TTTC Senior Past Chair
   
9:10-9:50 Keynote 1:  The Future Is Low Power and Test
  T.W. WILLIAMS (Synopsys Fellow - USA)
 
9:50-10:30 Keynote 2: The Role of Test in Circuits Built with Unreliable Components
  Antonio RUBIO (Technical University of Catalonia, UPC - Spain)
  top
10:30-11:00 Coffee Break
11:00-12:30
Sala Toscanini
  Session 2A: Testing and Monitoring for High Quality Requirements

Moderators: John P. HAYES (University of MichiganUSA),
Kewal SALUJA (University of Wisconsin-Madison - USA)
 
» Safe Fault Collapsing Based on Dominance Relations
Irith POMERANZ (Purdue University - USA), 
Sudhakar REDDY (University of Iowa - USA)
   
» A Reliable Architecture for the Advanced Encryption Standard
Giorgio DI NATALE (LIRMM - France),
Marion DOULCIER (LIRMM - France),
Marie-Lise FLOTTES (LIRMM - France),
Bruno ROUZEYRE (LIRMM - France) 
   
» An Embedded Test & Health Monitoring Strategy for Detecting and Locating Faults in Aerospace Bus Systems
Jari HANNU (University of Oulu - Finland), 
Denis KOLTSOV (Lancaster University – UK)
Zhou XU (Lancaster University - UK), 
Andrew RICHARDSON (Lancaster University - UK),
Markku MOILANEN (University of Oulu - Finland) 
    top
11:00-12:30 Session 2B: SoC Infrastructure
Sala Intra Moderators: Jaan RAIK (Tallinn Technical University - Estonia),
Franc NOVAK (Jozef Stefan Institute - Slovenia)
 
» Bandwidth Analysis for Reusing Functional Interconnect as Test Access Mechanism
Ardy VAN DEN BERG (TU Delft - The Netherlands), 
Pengwei REN (TU Delft - The Netherlands), 
Erik Jan MARINISSEN (NXP Semiconductors - The Netherlands), 
Georgi GAYDADJIEV (TU Delft - The Netherlands), 
Kees GOOSSENS (NXP Semiconductors - The Netherlands) 
 
» Analog Test Bus Infrastructure for RF/AMS Modules in Core-Based Design 
Vladimir ZIVKOVIC (NXP Semiconductors - The Netherlands), 
Frank VAN DER HEYDEN (NXP Semiconductors - The Netherlands), 
Frans DE JONG (NXP semiconductors - The Netherlands), 
Guido GRONTHOUD (NXP Semiconductors - The Netherlands) 
 
» FPGA-based low-cost automatic test equipment for digital integrated circuits 
Luca MOSTARDINI (University of Pisa - Italy), 
Luca BACCIARELLI (University of Pisa - Italy),
Luca FANUCCI (University of Pisa - Italy), 
Lorenzo BERTINI (SensorDynamics AG - Italy), 
Marco TONARELLI (SensorDynamics AG - Italy), 
Marco DE MARINIS (SensorDynamics AG - Italy) 
  top
11:00-12:30
Sala Rotary
Vendor
Session 2C:
ATE Architectures
Moderators: Hans MANHAEVE (Qstar - Belgium), 
Davide APPELLO (STMicroelectronics - Italy) 
 
» A tester system architecture designed to fulfill the increasing test requirements of today’s and future SoCs 
Andree WEYH (Verigy - Germany) 
 
» The mobile phone device test challenge 
Luigi CAZZANIGA (Teradyne - Italy) 
 
» Aligning Academia With Leading Edge Semiconductor Test Technology 
Paul RODDY (Semiconductor Test Consortium - USA
  top
12:30-14:00   Lunch
14:00-15:30
Sala Toscanini
Session 3A: Advances in RF Testing
Moderators: Salvador MIR (TIMA – France),
Jose Luis HUERTAS DIAS (CNM – Spain)
 
» Confidence Estimation in Non-RF to RF Correlation-Based Specification Test Compaction
Nathan KUPP (Yale University - USA), 
Petros DRINEAS (RPI - USA), 
Mustapha SLAMANI (IBM - USA), 
Yiorgos MAKRIS (Yale University - USA)
   
» Built-in Test of Frequency Modulated RF
Transmitters Using Embedded Low-Pass Filters
Rajarajan SENGUTTUVAN (Georgia Institute of Technology - USA), 
Abhijit CHATTERJEE (Georgia Institute of Technology - USA), 
Hyun CHOI (Georgia Institute of Technology - USA), 
DONGHOON HAN (Georgia Institute of Technology - USA)
   
» Using temperature as observable of the frequency response of RF CMOS Amplifiers
Josep ALTET (Universitat Politecnica de Catalunya - Spain), 
Eduardo ALDRETE-VIDRIO (Universitat Politecnica de Catalunya - Spain), 
Diego MATEO (Universitat Politecnica de Catalunya - Spain), 
Antonio RUBIO (Universitat Politecnica de Catalunya - Spain), 
Stefan DILHAIRE (Université Bordeaux I - France), 
Stephane GRAUBY (Université Bordeaux I - France)
   top
14:00-15:30
Sala Intra
Session 3B: Safe Test Generation and Design Validation
Moderators: Bernd STRAUBE (Fraunhofer IIS/EAS Dresden - Germany), 
Franco FUMMI (University of Verona - Italy)
   
» A Capture-Safe Test Generation Scheme for At-Speed Scan Testing
Xiaoqing WEN (Kyushu Institute of Technology - Japan), 
Kohei MIYASE (Kyushu Institute of Technology - Japan), 
SEIJI KAJIHARA (Kyushu Institute of Technology - Japan), 
Hiroshi FURUKAWA (Kyushu Institute of Technology - Japan), 
Yuta YAMATO (Kyushu Institute of Technology - Japan), 
Kenji NODA (Semiconductor Technology Academic Research Center - Japan), 
Hideaki ITO (STARC - Japan), 
Kazumi HATAYAMA (Semiconductor Technology Academic Research Center - Japan), 
Takashi AIKYO (Semiconductor Technology Academic Research Center - Japan), 
Kewal SALUJA (University of Wisconsin-Madison - USA)
   
» Temporally Extended High-Level Decision Diagrams for PSL Assertions Simulation
Maksim JENIHHIN (Tallinn University of Technology - Estonia), 
Jaan RAIK (Tallinn Technical University - Estonia), 
Anton CHEPUROV (Tallinn University of Technology - Estonia), 
Raimund UBAR (Tallinn Technical University - Estonia)
   
» On Bypassing Blocking Bugs during Post-Silicon Validation
Ehab ANIS DAOUD (McMaster University - Canada), 
Nicola NICOLICI  (McMaster University - Canada)
  top
14:00-15:30
Sala Rotary
Vendor
Session 3C:
Parallel Testing
Moderators: Luigi CARRO (UFRGS – Brazil), 
Anton CHICHKOV (AMIS – Belgium)
   
» New High Parallel RF Device Test Concept
Gary SHEEDY (Advantest GmbH - Germany), 
   
» Innovative approach to Reliability and Test Solutions exploiting DfT on Low-cost Massively Parallel Testers
Massimiliano GIANCARLINI (ELES Semiconductor Equipment - Italy), 
Roger CAGLIESI (ELES Semiconductor Equipment - Italy), 
Sandro GIORGI (ELES Semiconductor Equipment - Italy), 
Domenico CHINDAMO (Independent Consultant - Italy)
   
» Very High parallelism Test Cell for Sensors
Luciano BONARIA (Spea - Italy)
 top
15:30-16:30 Session 4: Posters and Coffee Break
   
» Proactive diagnostics of solder interconnection failures with embedded precursor monitoring
Juha VOUTILAINEN (University of Oulu - Finland), 
Jussi PUTAALA (University of Oulu - Finland), 
Markku MOILANEN (University of Oulu - Finland), 
Heli JANTUNEN (University of Oulu - Finland) 
 
» Test Generation for Maximal Crosstalk Noise
Minjin ZHANG (Chinese Academy of Sciences - China), 
Huawei LI (Chinese Academy of Sciences - China), 
Xiaowei LI (Chinese Academy of Sciences - China) 
 
» Software-Based BIST Capabilities of the Advanced Encryption Standard
Paolo MAISTRI (TIMA Laboratory - France), 
Regis LEVEUGLE (TIMA Laboratory - France), 
Cyril EXCOFFON (TIMA Laboratory - France) 
 
»  TTR+V: Triple Time Redundancy Plus Voting – A New Fault Masking Scheme for Multi-Context FPGAs
Markus HOLZ (Leibniz Universität Hannover - Germany), 
Erich BARKE (Leibniz Universität Hannover - Germany) 
 
» Exploiting Volume Diagnosis Data Filtering for Yield Learning
Davide APPELLO (STMicroelectronics - Italy),  
Thomas WILLIAMS (Synopsys - USA),
Emil GIZDARSKI (Synopsys - USA), 
Vincenzo TANCORRE (STMicroelectronics - Italy), 
Paul TODARO (Synopsys - USA), 
Salvatore TALLUTO (Synopsys - USA), 
Giuseppe DE NICOLAO (Università di Pavia - Italy), 
Paolo AMATO (STMicroelectronics - Italy) 
 
» Advanced Digital Signal Inspector for the analysis of internal signals in pin-limited Systems-on-Package
Luca BACCIARELLI (Università di Pisa - Italy), 
Luca MOSTARDINI (Università di Pisa - Italy),  
Luca FANUCCI (Università di Pisa - Italy),
Christian ROSADINI (SensorDynamics AG - Italy), 
Alessandro ROCCHI (SensorDynamics AG - Italy), 
Marco DE MARINIS (SensorDynamics AG - Italy), 
Luca BENVENUTI (Università di Pisa - Italy) 
 
» A Novel Transient Fault Injection Method Based on STE Model Checking
Ashish DARBARI (Southampton University - UK),
Bashir AL-HASHIMI (Southampton University - UK), 
Peter HARROD (ARM Ltd. – UK), 
Daryl BRADLEY (ARM Ltd. – UK) 
 
» Bidirectional Delay Test of FPGA Routing Networks
Elena HAMMARI (NTNU - Norway), 
Michiko INOUE (Nara Institute of Science and Technology - Japan), 
Einar J AAS (NTNU - Norway), 
Hideo FUJIWARA (Nara Institute of Science and Technology - Japan) 
 
» An Efficient Test and Characterization Approach for Nanowire-Based Architectures
Eduardo RHOD (UFRGS - Brazil),
Luigi CARRO (UFRGS - Brazil), 
Erika COTA (UFRGS - Brazil) 
   
» On Design of Hold Scan Cell for Hybrid Operation of a Circuit
Hyunbean YI (UMass - USA), 
Sandip KUNDU (University of Massachusetts - USA) 
 
» The (Black) Art of Optimizing Test Vector Generation
Hans MANHAEVE (Q-Star Test - Belgium), 
Stefaan KERCKENAERE (Q-Star Test - Belgium), 
Geir EIDE (Magma Design Automation Inc. - USA), 
Juraj BRENKUS (STU-Bratislava - Slovakia) 
  top
16:30-18:00
Sala Toscanini
Session 5A: News from Memory Test
Moderators: Said HAMDIOUI (TU Delft – The Netherlands),
Paul HUGUES (ARM Inc. – USA)
  
» Applying March Tests to K-Way Set-Associative Caches
Stefano DI CARLO (Politecnico di Torino - Italy), 
Paolo PRINETTO (Politecnico di Torino - Italy), 
Alessandro SAVINO (Politecnico di Torino - Italy), 
Simone ALPE (Politecnico di Torino - Italy)
 
» Hierarchical code correction and reliability management in embedded NOR flash memories
Benoit GODARD (Atmel Rousset - France), 
Jean Michel DAGA (Atmel Rousset - France), 
Lionel TORRES (LIRMM - France), 
Gilles SASSATELLI (LIRMM - France) 
   
» Self-Programmable Shared BIST for Testing Multiple Memories
Swapnil BAHL (STMicroelectronics - India), 
Vishal SRIVASTAVA (STMicroelectronics - India
  top
16:30-18:00
Sala Intra
Session 5B: Diagnosis: New Concepts and Industrial Application
Moderators: Helmut LANG (Freescale Semiconductor – Germany),
Bruno ROUZEYRE (LIRMM – France)
  
» Bridge Defect Diagnosis for Multiple-Voltage Design
S. Saqib KHURSHEED (University of Southampton - UK), 
Paul M ROSINGER (University of Southampton - UK), 
Bashir AL-HASHIMI (University of Southampton - UK), 
Sudhakar REDDY (University of Iowa - USA), 
Peter HARROD (ARM LTD - UK)
  
» Diagnose Multiple Stuck-at Scan Chain Faults
Yu HUANG (Mentor Graphics Corp. - USA), 
Wu-Tung CHENG (Mentor Graphics Corp. - USA), 
Ruifeng GUO (Mentor Graphics Corp. - USA)
  
» Increased Fault Diagnosis Throughput Using Dictionary for Hyperactive Faults
Chen LIU (University of Iowa - USA), 
Wu-Tung CHENG (Mentor Graphics Corp. - USA), 
Huaxing TANG (Mentor Graphics Corp. - USA), 
Sudhakar REDDY (University of Iowa - USA), 
Wei ZOU (Mentor Graphics Corp. - USA), 
Manish SHARMA (Mentor Graphics Corp. - USA)
  top
16:30-18:00
Sala Rotary
Vendor
Session 5C:
The Power of DfT
Moderators: Magdy ABADIR (Freescale – USA),
Carsten WEGENER (Infineon – Germany)
 
» Paving the way to 1000X compression
Greg ALDRICH (Mentor Graphics Corp. - USA)
 
» Power - The new dimension of test
Richard ILLMAN (Cadence Designs Systems - USA)
Michael O'SULLIVAN (Cadence Designs Systems - USA)
 
» Low Power Test Methodologies
Nikolaus MITTERMAIER (Synopsys GmbH - Germany)
  top
18:00-19:30
Sala Toscanini
Panel
Session 6A:
Commercial tools for RTL Design-for-Test exist but how good are they?
Organizer: Erik LARSSON (Linköpings University - Sweden)
Moderator: Nicola NICOLICI (McMaster University - Canada)
 
Abstract: Design for Testability on RT-level descriptions has been extensively explored by academia as a research domain in the past decade, and now commercial tools are finally on the market, and start to be used in industrial design flows. The panel aims at gathering different opinions on these tools and on their future evolution: are they welcome from industry? How much are they effective? How well do they fit in the existing design flows? Which are the expectations for new techniques and tools? What is likely feasible, and what is simply a dream?      
 
Panelists:
»

Chouki AKTOUF (DeFacTo Technologies - France),

»

Wu-Tung CHENG (Mentor Graphics Corp. - USA),

»

Prab VARMA (BluePearl Software - USA),

»

Kewal SALUJA (University of Wisconsin-Madison - USA),

»

Matteo SONZA REORDA (Politecnico di Torino - Italy),

» Sandeep GOEL (Magma Design Automation Inc. - USA)
  top
18:00-19:30
Sala Intra
Panel
Session 6B:
No Beginners Beyond this Point
Organizer: Erik Jan MARINISSEN (NXP - The Netherlands)
Moderator: Adit SINGH (Auburn UniversityUSA)
 
Abstract: Semiconductor process technologies continue to scale down, and hence become more sensitive for even the smallest disturbances. In addition, new transistor designs and the introduction of exotic new materials cause new, unfamiliar defect modes. And as design complexity grows, there are more potential locations for failure. Despite all these trends, it seems that customers are only increasing their expectations with respect to product quality. Design-for-Yield is a popular buzzword, but right now, test is still needed to help us meet these quality requirements. Can the test community keep up with the fast-forward mode of process technology and design? What is the best test approach now, and in the future, and does self-healing play a role in that? Will only companies that invest heavily in advanced test methods survive? Or is fault-tolerance our future?
 
Panelists:
» Rob AITKEN (ARM - USA),
» Dan GLOTTER (OptimalTest - Israel),
» Carlo GUARDIANI (PDF Solutions - Italy),
» Peter MUHMENTHALER (Infineon - Germany),
» Keith ARNOLD (Pintail Technologies - USA)
  top
May 27th, 2008
08:30-10:00
Sala Toscanini
Session 7A: Delay Faults: Simulation, Test Generation and DFT Moderator
Moderators: Seiji KAJIHARA (Kyushu Institute of Technology – Japan),
Arnaud VIRAZEL (LIRMM – France)
 
»  A Simulator of Small-Delay Faults Caused by Resistive-Open Defects 
Alejandro CZUTRO (University of Freiburg - Germany), 
Nicolas HOUARCHE (LIRMM - France), 
Piet ENGELKE (University of Freiburg - Germany),  
Ilia POLIAN (University of Freiburg - Germany), 
Mariane COMTE (LIRMM - France), 
Michel RENOVELL (LIRMM - France), 
Bernd BECKER (University of Freiburg - Germany)
 
» Critical Path Selection For Delay Test Considering Coupling Noise
RAJESHWARY TAYADE (University of Texas - USA),  
Jacob ABRAHAM (University of Texas - USA)
 
» Low Overhead Partial Enhanced Scan Technique
for Compact and High Fault Coverage Transition Delay
Test Patterns
  
Seongmoon WANG (NEC Labs America - USA), 
Wenlong WEI (NEC Labs America - USA)
 top
08:30-10:00
Sala Intra
Session 7B: SoC Testing
Moderators: Sandeep K. GOEL (Magma Design Automation – USA),
Mounir BENABDENBI (LIP6 – France)
 
» Accelerated Shift Registers for X-tolerant test data compaction
Martin HILSCHER (University of Potsdam - Germany),
Michael BRAUN (VERIGY - Germany),
Michael GOESSEL (University of Potsdam - Germany),
Michael RICHTER (University of Potsdam - Germany),
Andreas Leininger (Infineon Technologies AG - Germany)  
 
» A new description language for SoC testing
Michele PORTOLAN (Alcatel-Lucent Bell Labs - Ireland),
Suresh GOYAL (Alcatel-Lucent Bell Labs - USA),  
Bradford G. VAN TREUREN (Lucent Technologies - USA), 
Chen-Huan CHIANG (Lucent Technologies - USA), 
Tapan CHAKRABORTY (Alcatel-Lucent Bell Labs - USA), 
Tom COOK (Alcatel-Lucent Bell Labs - USA)
 
» An Innovative and Low-Cost Industrial Flow for Reliability Characterization of SoCs
Davide APPELLO (STMicroelectronics - Italy)
Paolo BERNARDI (Politecnico di Torino - Italy), 
Michelangelo GROSSO (Politecnico di Torino - Italy), 
Roger CAGLIESI (ELES Semiconductor Equipment - Italy), 
Massimiliano GIANCARLINI (ELES Semiconductor Equipment - Italy),
  top
08:30-10:00
Sala Rotary
Vendor
Session 7C:
Potpourri
Moderators: Erik Jan MARINISSEN (NXP Semiconductors - The Netherlands),
Ilia POLIAN (University of Freiburg - Germany)
 
» Overcoming the PCI Express debugging Nightmare 
Vincenzo DI CIANNI (VSYSTEMS SRL - Italy) 
 
» Current Test Application Perspective 
Hans MANHAEVE (Q-Star Test nv - Belgium) 
 
» The Role of Silicon Aware IP in Shortening Time-to-Volume
Yervant ZORIAN (Virage Logic - USA) 
     top
10:00-11:00 Session 8: Posters and Coffee Break
   
»  A Multi-Tone Signal Generation Technique for Production Test
Sadok AOUINI (McGill University - Canada), 
Gordon ROBERTS (McGill University - Canada)
   
» Robust Tests for Transition Faults with Long Propagation Paths Using Boolean Satisfiability
Stephan EGGERSGLüß (University of Bremen - Germany), 
Daniel TILLE (University of Bremen - Germany), 
Rolf DRECHSLER (University of Bremen - Germany)
   
» Implementation of linear histogram based ADC testing, a case study
Peter MRAK (Jozef Stefan Institute - Slovenia), 
Anton BIASIZZO (Jozef Stefan Institute - Slovenia), 
Franc NOVAK (Jozef Stefan Institute - Slovenia)
   
» SET-Factor: An Analysis and Design Tool to Reduce SET Sensitivity in Integrated Circuits
Fernanda KASTENSMIDT (UFRGS - Brazil), 
Cristiano LAZZARI (CEITEC - Brazil), 
Thiago ASSIS (UFRGS - Brazil), 
Ricardo REIS (Instituto de Informatica - Brazil), 
Lorena ANGHEL (TIMA Laboratory - France), 
Gilson WIRTH (UFRGS - Brazil)
   
» Design Methodology of Analog/Mixed-Signal Circuits For Yield Enhancement
Luo PEI-WEN (Industrial Technology Research Institute - Taiwan), 
Chen JWU-E (Department of Electrical Engineering National Central University - Taiwan), 
Wey CHIN-LONG (Department of Electrical Engineering National Central University - Taiwan), 
Liang HSING-CHUNG (Department of Electronic Engineering Chang Gung University - Taiwan), 
Chen JI-JAN (SoC Technology Center Industrial Technology Research Institute - Taiwan), 
Cheng LIANG-CHIA (SoC Technology Center Industrial Technology Research Institute - Taiwan)
  
» An efficient Diagnosis Methodology for analog blocks: Application to Current Reference Circuits
Hassen AZIZA (L2MP - France), 
Jean Michel PORTAL (L2MP/Polytech - France), 
Olivier GINEZ (L2MP - France), 
Emmanuel BERGERET (L2MP - France)
 
» Fault Models and Injection Strategies for a Reflective Simulation Platform
Antonio MIELE (Politecnico di Milano - Italy), 
Cristiana BOLCHINI (Politecnico di Milano - Italy), 
Donatella SCIUTO (Politecnico di Milano - Italy)
   
» Novel Analog DFT for Data Retention Fault and Weak Cell Detection for SRAM Memories
Mohamed AZIMANE (NXP Semiconductors - The Netherlands), 
Bram KRUSEMAN (NXP Semiconductors - The Netherlands), 
Ananta MAJHI (NXP Semiconductors - The Netherlands)
 
» Identification of dynamic faults in interconnects by the use of polynomial algebra
Michal KOPEC (Silesian University of Technology - Poland), 
Tomasz GARBOLINO (Silesian University of Technology - Poland), 
Krzysztof GUCWA (Silesian University of Technology - Poland), 
Andrzej HLAWICZKA (Silesian University of Technology - Poland)
 
» An IEEE P1687 Instrument for the Concurrent Testing of IEEE 1500 Wrapped Cores
Michael HIGGINS (University of Limerick - Ireland)
  top
11:00-12:30
Sala Toscanini
Session 9A: On-Chip Resources for Mixed-Signal Devices
Moderators: Yiorgos MAKRIS (Yale UniversityUSA),
Abhijit CHATTERJEE (Georgia Tech. - USA)
 
»  Utilizing On-Chip Resources for Testing Embedded Mixed-Signal Cores
Carsten WEGENER (Infineon Technologies AG - Germany), 
Heinz MATTES (Infineon Technologies AG - Germany), 
Stephane KIRMSER (Infineon Technologies AG - Germany), 
Frank DEMMERLE (Infineon Technologies AG - Germany), 
Sebastian SATTLER (Infineon Technologies AG - Germany)
 
» An Improved Algorithm to Identify the Test Stimulus in Histogram-Based A/D Converter Testing
Esa KORHONEN (University of Oulu - Finland), 
Juha KOSTAMOVAARA (University of Oulu - Finland)
 
» Utilizing On-chip generation of sine-wave signals for low cost functional test
Miguel DOMINGUEZ (University of Extremadura - Spain),
Jose Luis AUSIN (University of Extremadura - Spain), 
Guido TORELLI (University of Pavia - Italy), 
Juan DUQUE-CARRILLO (University of Extremadura - Spain)
  top
11:00-12:30
Sala Intra
Special
Session 9B:
NASA Flatsats: Spacecraft Testbeds for Mission Success
Organizer: Michael WRIGHT (NASA - USA)
Moderator: Yervant ZORIAN (Virage Logic – USA)
 
Abstract: This special session will address electronics testbeds (“flatsats”) that have been developed by NASA Goddard Space Flight Center (GSFC) for testing spacecraft avionics and software. Flatsats from a range of “in-house” flight projects will be discussed, representing past and current missions: Lunar Reconnaissance Orbiter (LRO), Solar Dynamics Observatory (SDO), Space Technology -5 (ST-5), and Microwave Anisotropy Probe (MAP). The session will consist of brief presentations on the flatsat concept and descriptions of each project, followed by a question-and-answer period. Topics to be presented include: mission overview, purpose and requirements of the flatsat system, functional description, benefits to respective projects, and any lessons learned.   
 
Speakers:
»

Michael WRIGHT (NASA - USA)

»

David AMASON (NASA - USA)

»

Steven THIBAULT (JHU/APL - USA)

» Peter HARVEY (UC Berkeley - USA)
  top
11:00-12:30
Sala Rotary
Vendor
Session 9C:
Test Engineering
Moderators: Sandip KUNDU (Univ. of Massachusetts Amherst - USA), 
Wu-Tung CHENG ( Mentor Graphics - USA)
 
» Effective DPPM improvement programs require test program qualification and post-probe data analysis
Frederic TILHAC (Test Advantage, Inc. - France) 
 
» Observability of production test
Meir GELLIS (TestInsight - Israel) 
 
» What if you could... join NXP?
Winston Sarrucco (NXP Semiconductors - The Netherlands) 
   top
12:30-14:00     Lunch
 
14:00-15:00
Sala Toscanini
Embedded Tutorial Session 10A: Post-Silicon Validation and Debug   
Moderator: Prab VARMA (BluePearl Software – USA)
 
Abstract: Pre-silicon verification methods work with models of the design and are therefore limited by the inherent trade-off between their accuracy and the associated simulation time. Designs are sent to fabrication when the confidence level seems high enough; unfortunately, it still happens that functional and electrical design errors remain undetected in pre-silicon verification and slip through to prototype silicon. Errors that slip through require fixing as soon as possible once detected on the prototype. Hence, the pre-silicon verification transitions to post-silicon validation and debug upon return of first silicon samples from the factory. The continued need for more effective and efficient debugging methods and instruments is expected to drive innovative and new debug research over the forthcoming years. In this tutorial, we present the fundamentals of this field, as well as give an overview of some recent advances in debug research and development. Topics to be covered include functional/electrical design errors, run-stop debugging, real-time functional observability, embedded instrumentation, integrated logic analysis, transaction-based debug, and integrated hardware/software debug. This tutorial is intended to stimulate people into starting research and development work in this exciting field.
 
Speakers:
»  Bart VERMEULEN (NXP Semiconductors – The Netherlands), 
» Nicola NICOLICI (McMaster University - Canada)
  top
14:00-15:00
Sala Intra
Embedded Tutorial Session 10B: Update: the P1687 (IJTAG) Hardware Proposal for Efficient Embedded Instrument Access, Bandwidth, and Connectivity – the ABC’s of Embedded Content 
Moderator: Rob AITKEN (ARM – USA) 
 
Abstract: Modern ICs have achieved a level of complexity where simple ATE test is not enough to determine if the part was designed and manufactured correctly – and modern packaging such as known good die and stacked die severely complicate the embedded landscape. More and more ICs are including Functional configuration choices; Debug logic (DFD); Test logic (DFT); manufacturing process and environment monitors (DFM); and yield-analysis support logic (DFY) – these logics need to be accessed at wafer probe, at package test, at board test, and even in-system. In the past, this logic was usually targeted at only one use environment and with ad hoc consideration for access – today these logics must interact with each other and they require formal scheduling and cataloguing to enable access, configuration, and operation that will fit within engineering budgets, cost and time budgets, and test equipment resource budgets. This embedded tutorial will show the multiple defined instrument interfaces to meet the access needs of various instruments; the connection schemes that can be applied versus engineering budgets such as area, routing, power, and access efficiency; the proposed high-bandwidth data connections that will allow high data-volume, targeted instrument latency, and instrument-to-instrument communication; and how all of this falls within the operating arena of the 1149.1 JTAG TAP and TAP Controller.
 
Speakers:
» Alfred CROUCH (Inovys - USA),
» Jeff REARICK (AMD - USA),
» Ken POSSE (AMD - USA)
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14:00-15:00
Sala Rotary
Embedded Tutorial Session 10C: DFT/BIST Circuit Techniques Using Sigma-Delta Encoding Methods
Moderator:   Adam OSSEIRAN (Edith Cowan University – Australia)
 
Abstract: This tutorial will look at different ways in which sigma-delta techniques can be used for DFT and BIST. One section will describe varous methods in which to generate high-precision analog signals, such as DC, sinusoids, multi-tones, Gaussian noise signals, phase and frequency modulated signals, etc. Such methods have application for retrofitting digital testers as mixed-signal testers, as well as extending the capability of existing mixed-signal testers. Subsequently, we’ll demonstrate how sigma-delta methods can be used in a wide range of DFT/BIST circuits for SOC applications. This will include signal sources, digitizers, coherent samplers, time-domain reflectometry and transmission, and noise and jitter analyzers.
 
Speaker:
» Gordon Roberts (McGill UniversityCanada)  
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16:00     Social Program
May 28th, 2008
08:30-10:00
Sala Toscanini
Session 11A: Solutions for Yield Enhancement
Moderators: Joan FIGUERAS (UPC - Spain), 
  Ricardo REIS (UFRGS – Brazil)
 
»  Identifying Physical Root Causes for Yield Excursions from Test Fail Data
Manish SHARMA (Mentor Graphics Corp. - USA), 
Brady BENWARE (Mentor Graphics Corp. - USA), 
Martin KEIM (Mentor Graphics Corp. - USA), 
Huaxing TANG (Mentor Graphics Corp. - USA), 
I.Y. CHANG (UMC - Taiwan), 
Albert MAN (AMD - Canada)
 
» When physical fault clustering meets pattern fault clustering
Jan SCHAT (NXP - Germany)
 
» Jitter Decomposition in High Speed Communication Systems
Qingqi DOU (University of Texas - USA), 
Jacob ABRAHAM (University of Texas - USA)
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08:30-10:00
Sala Intra
Session 11B: Online Checking
Moderators: Lorena ANGHEL (TIMA - France), 
Sandeep GUPTA (USC – USA)
 
» Risks for Signal Integrity in System in Package and Possible Remedies
Daniele ROSSI (Università di Bologna - Italy), 
Paolo ANGELINI (Università di Bologna - Italy), 
Cecilia METRA (Università di Bologna - Italy), 
Giovanni CAMPARDO (STMicroelectronics - Italy), 
Gian Pietro VANALLI (STMicroelectronics - Italy) 
 
» Detecting Multi-cycle Errors using Invariance Information
Nuno ALVES (Brown University - USA), 
Kundan NEPAL (Bucknell University - USA), 
Bryant MAIRS (Brown University - USA), 
JENNIFER DWORAK (Brown University - USA), 
Iris BAHAR (Brown University - USA)
 
» Function Inherent Code Checking: A New Low Cost On-Line Testing Approach For High Performance Microprocessor Control Logic
Cecilia METRA (Università di Bologna - Italy),
Daniele ROSSI (University of Bologna - Italy),
Martin Eugenio OMANA (University of Bologna - Italy),
Abhijit JAS (Intel Corporation - USA),
Rajesh GALIVANCHE (Intel Corporation - USA)
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08:30-10:00
Sala Rotary
Vendor
Session 11C:
Design-for-Test
Moderators: Srikanth VENKATARAMAN (Intel – USA), 
Ondrej NOVAK (Czech Technical Univ. - Czech Republic)
 
» Scan-Through-TAP: Combining Scan Chain and Boundary Scan Features in SOC
Zoran STAMENKOVIC (IHP - Germany), 
Mary GILES (Synopsys Inc. - USA), 
Francisco RUSSI (Synopsys Inc. - USA)
 
» Inserting DFT at RTL Becomes Real
Chouki AKTOUF (DeFacTo Technologies - France)
 
» Physical-Aware ATPG: What Does It Really Mean?
SANDEEP GOEL (Magma Design Automation - USA), 
Geir EIDE (Magma Design Automation - USA), 
Robert THOMPSON (Magma Design Automation - USA)
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10:00-11:00 Session 12: Posters and Coffee Break
 
» A Temperature and Power Supply Independent CMOS Voltage Reference for Built-In Self-Test
Luca TESTA (IMS Laboratory - France), 
MIKAEL CIMINO (IXL Laboratory - France), 
Herve LAPUYADE (IXL Laboratory - France), 
Yann DEVAL (IMS Laboratory - France), 
Jean-Louis CARBONERO (STMicroelectronics - France), 
Jean-Baptiste BEGUERET (IMS Laboratory - France)
 
» Improved Circuit-to-CNF Transformation for SAT-based ATPG
Daniel TILLE (University of Bremen - Germany),  
Rene KRENZ-BAATH (NXP Semiconductors GmbH - Germany), 
Juergen SCHLOEFFEL (Philips Semiconductors GmbH - Germany), 
Rolf DRECHSLER (University of Bremen - Germany)
 
» Design-for-Debug Architecture for Distributed Embedded Logic Analysis
Ho Fai KO (McMaster University - Canada), 
Adam KINSMAN (McMaster University - Canada), 
Nicola NICOLICI (McMaster University - Canada)
 
» Timing Yield Modeling Based on Simulation of Lithography Process
Aswin SREEDHAR (University of Massachusetts - USA), 
Sandip KUNDU (University of Massachusetts - USA)
 
» Diagnosis of Multiple Scan Chain Failures
Nadir BASTURKMEN (Intel - USA), 
Ruifeng GUO (Mentor Graphics Corp. - USA), 
Srikanth VENKATARAMAN (Intel Corporation - USA)
 
» SystemC-based Fault Injection Technique with Improved Fault Representation 
Rishad SHAFIK (University of Southampton - UK), 
Paul M ROSINGER (University of SouthamptonUK), 
Bashir AL-HASHIMI (University of SouthamptonUK)
 
» Efficient scheduling of delay tests for latch-based circuits
Kun Young CHUNG (University of Southern California - USA), 
Sandeep GUPTA (University of Southern California - USA)
 
» Shrinking the Application Time of Test Set Embedding by Using Variable-State Skip LFSRs
Vasilios TENENTES (University of Ioannina - Greece), 
Kavoisianos CHRISOVALANTIS (University of Ioannina - Greece), 
Emmanouil KALLIGEROS (University of Patras - Greece)
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11:00-12:30
Sala Toscanini
Embedded Tutorial
Session 13A:
Reliability, Availability and Serviceability of Networks-on-Chip
Moderator: Gert Jervan (Tallinn University of Technology – Estonia)
 
Abstract: This tutorial presents an overview of the issues related to the test, diagnosis and fault-tolerance of NoC-based systems. First, the characteristics of the NoC design (topologies, structures, routers, wrappers, and protocols) are presented, as well as a summary of the terms used in the field and an overview of the existing industrial NoCs is given. Then, the challenges to test, diagnose and tolerate faults in a NoC-based system are discussed. Current test strategies are then presented: re-use of on-chip network for core testing, test scheduling for the NoC reuse, test access methods and interface, efficient re-use of the network, and power-aware and thermal-aware testing. In addition, the challenges and solutions for the NoC (interconnects, routers, and network interface) test and diagnosis are presented. Finally, since quality-of-service is one of the main challenges for the NoC use, fault tolerance techniques for the NoC are discussed.  
 
Speakers:
» Erika COTA (UFRGS - Brazil),
» Marcelo LUBASZEWSKI (UFRGS - Brazil)
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11:00-12:30
Sala Intra
Special
Session 13B:
Collaborative Test Research in Europe
Organizer: Hans-Joachim WUNDERLICH (Universität Stuttgart - Germany)
Moderator: Hans-Joachim WUNDERLICH (Universität Stuttgart - Germany)
 
Abstract: Representatives of large national and international joint research projects in the area of test will share their experiences. The benefits and the technical results, the added value of joint research and the organisation and administration of large projects as well as the presentation and evaluation of the research results will be discussed. Furthermore, topics and possibilities of future joint projects will be investigated under both technical and organizational aspects.  
 
Speakers:
» Kees VEELENTURF (NANOTEST, NXP – The Netherlands)
» Sybille HELLEBRAND (REALTEST, University of Paderborn - Germany)
» Andrew RICHARDSON (NoE Patent-DfMM, University of Lancaster - UK)
» Peter MUHMENTHALER (Infineon - Germany)
» Michel BURLE (Medea Office - France)
» Paul RODDY (ITRS, Advantest - USA)
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12:30-14:00 Lunch
14:00-15:30
Sala Toscanini
Session 14: Soft Error Mitigation
Moderators: Matthias PFLANZ (IBM – Germany), 
Virendra SINGH (IISc Bangalore – India)
 
» Selective Hardening in Early Design Steps 
Christian ZOELLIN (Universität Stuttgart - Germany),
Hans-Joachim WUNDERLICH (Universität Stuttgart - Germany), 
Ilia POLIAN (University of Freiburg - Germany), 
Bernd BECKER (University of Freiburg - Germany)
 
» Tunable transient filters for soft error rate reduction in combinational circuits
Quming ZHOU (Rice University - USA), 
Mihir CHOUDHURY (RiceUniversity - USA), 
Kartik MOHANRAM (Rice University - USA)
 
» Convolutional coding for SEU mitigation
Laura FRIGERIO (Politecnico di Milano - Italy), 
Matteo RADAELLI (Politecnico di Milano - Italy), 
Fabio SALICE (Politecnico di Milano - Italy)
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15:30-16:00
Sala Toscanini
Session 15: Closing Remarks and Introduction to ETS’09
 
» Closing Remarks
Matteo SONZA REORDA (Politecnico di Torino - Italy)
ETS’08 General Chair
 
» Introduction to ETS’09
Jose Luis HUERTAS DIAS (CNM, Seville - Spain)
ETS’09 General Chair
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