13th IEEE European Test Symposium
Verbania, ITALY, May 25-29, 2008

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  ETS'08 - Tutorials  

The tutorials of ETS'08 are part of the annual IEEE Computer Society TTTC Test Technology Educational Program (TTEP) 2008

The tutorials will take place on Sunday, May 25th, from 9:00 till 17:00. Tutorials will be held in the Hotel Il Chiostro, which is located about 2 Km from the Hotel Majestic (where ETS will be held). Please refer to the map for the location of the tutorial site.

A bus service will be available from Hotel Il Chiostro to Hotel Majestic, and back. Click here for more info.

Tutorial registration is done via the ETS Registration Form.

Please find below the description of Tutorial 1 and Tutorial 2

  • Tutorial 1: DFx: The convergence of test, manufacturing, and yield
  • Tutorial 2: IEEE 1500 - Building a Compliant Wrapper
Tutorial 1

DFx: The convergence of test, manufacturing, and yield

Author and Presenter:
Robert AItken, ARM Sunnyvale, CA, USA 

Intended Audience:
Test practitioners (engineers, students, academics) who are interested in learning more about the interaction between design and test, as they relate to yield, manufacturability and variability, and how they will affect chips in sub-90nm process technology.

The tutorial goal is to show how design for yield (DFY) and design for manufacturability (DFM) are tightly coupled into what we conventionally think of as test, and that as process geometries shrink, the line between defects and process variation blurs to the point where it is essentially non-existent. In DFM/DFY circles, it is common to speak of defect limited yield, but it is less common to think of test-limited yield, yet this concept is common in DFT (e.g. IDDQ testing, delay testing). This tutorial will provide background needed for DFT practitioners to understand DFM and DFY, and see how their work relates to it. The ultimate goal is to spur attendees to conducting their own research in the area, and to apply these concepts in their jobs.

 Program Outline:
1 Introduction and background (60 min)
Tutorial goal What is DFX? Interaction of manufacturability, yield, variability, and test Photolithography basics Resolution enhancement technology

 2 Design for manufacturability (90 min)
Basic techniques of DFM Lithography: DRC rules, recommendations, shape-based effects, process window, simulation Critical area: shorts/opens/vias/contacts, inductive fault analysis, tradeoffs, optimization, CMP:analysis, density rules, systematic versus random components Tradeoffs: metrics, competing effects, the challenge of yield, design intent

 3 Yield (90 min)
Manufacturability versus yield Yield models and metrics Poisson, negative binomial, Murphy, ... Economics of yield Classes of yield Systematic Parametric Defect-related Design-related Redundancy/Repair Memory and logic Process monitors and data collection SRAM-based, feature-based, ring oscillators

 4 Variability (60 min)
Design margin versus characterization Statistical behavior Timing models path-based block-based
Extreme value theory

 5 Test and reliability (40 min)
Diagnosis and failure analysis Variability and defects Small delay defects Correlation, test, and measurement Reliability issues repair, aging, burn-in, materials

 6 Putting it all together (20 min)
Applying these techniques in your organization What works and what doesn't
Areas for future research

Tutorial 2

IEEE 1500 - Building a Compliant Wrapper

Teresa McLaurin, ARM Austin, TX USA;
Tom Waayers, NXP Eindhoven, The Nederlands;
Francisco Da Silva, NVidia Santa Clara, CA, USA;

Teresa McLaurin and Tom Waayers

Intended Audience:
This tutorial is for anyone who wants to understand the rules, the challenges and the benefits of IEEE 1500 core test wrapper standard and how it might be utilized to make test scheduling easier in an SoC.

The purpose of this tutorial is to educate the audience with the challenges and benefits associated with implementing IEEE 1500 compliant wrappers for Core Test. This tutorial will also give an understanding of the reasons behind some of the rules in the standard. A 1500 wrapper, with CTL, is built piece by piece around an example bare core for illustration purposes. The pros and cons of different choices that are available to the user of the 1500 standard are discussed. All rules are discussed. Integration of cores and
test scheduling in an SoC is also discussed.

The tutorial first discusses what a test wrapper is and why it is utilized. The advantages of standardization are also discussed, as well as wrapped compliancy versus unwrapped compliancy. After this, the example bare core is created. After completing this tutorial, the attendees will be able to implement an IEEE 1500 wrapper on most cores, due to the fundamentalinstruction that will be given in this tutorial. In addition, they will have a better understanding of CTL and the advantages of using the IEEE 1500 standard.

Mandatory and optional instructions are described. Instructions are chosen for the example core and the reasons for choosing these instructions are discussed.

 “Building the WBR”
The tutorial discusses how 1500 compliant wrapper cells are constructed, provide isolation at the core terminal level and allow test stimuli to be applied to wrapped terminals as well as allow test response to be captured from wrapped terminals. The tutorial shows standard operations for dedicated, shared and reduced functionality cells and for the WBR that is a collection of wrapper cells stitched into one or more scan chains inside the 1500 wrapper.

 “Building the WBY”
The tutorial describes the WBY and why it is mandated. A WBY is created for the example core.

 “Building the WIR”
The 1500 wrapper contains a standard mechanism for handling test control. This mechanism is called the Wrapper Instruction Register (WIR) and is implemented to configure the WBR and control the modes of the core embedded within the 1500 wrapper. This tutorial gives an in-depth overview of rules applying to the WIR, its architecture, implementation examples, configuration and standard protocol. For the example core this tutorial shows how WIR circuitry design is derived from the core’s test requirements.

 “Putting the Pieces Together”
After the WIR, WBR and WBY are constructed, they must be connected together. This section describes the logic needed to do this for the example core. In addition, hierarchical cores are discussed.
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Examples of how cores can be accessed and tests scheduled in an SOC are reviewed. 

I. What is a test wrapper? (15 min)

a) Why is a wrapper important?

 II. Brief high level description of the 1500 Wrapper (15 min)

a) Compliant – wrapped/unwrapped

i) hardware

ii) CTL

III.Why use the 1500 standard (advantages) (10 min)

a) automation can occur

b) 3rd party tools – to be used by core provider and user

c) Easier path from core to SoC (pattern changes, test logic instantiation)

d) Reduced pattern generation, silicon debug and diagnosis turnaround time for large designs

 IV. Building an IEEE Std. 1500 compliant wrapper (180 min)

a) Example core

b) Wrapper Interface Port

c) Instructions required/desired

i) types

ii) usage


c’) Building the WBR 

i) wrapper cells

ii) requirements of the core


d) Building the WBY 

i) Utilization and construction

ii) CTL

e) Building the WIR 

i) WIR requirements

ii) Requirements of this core


f) Putting the IEEE 1500 wrapper pieces together 

i) CTL

 V. Hierarchical Cores (15 min)

 VI. SOC Integration of 1500 Core (120 min)

a) Types of connections (serial/parallel)

b) Connecting a TAP to a 1500 wrapper

c) Test scheduling


 IEEE tttc
Computer Society Politecnico di Torino

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