Workshop on Low Power Design Impact on Test and
The IEEE InternationalWorkshop on Impact of Low
Power Design on Test and Reliability (LPonTR) aims to bring together design,
reliability and test engineers and researchers to discuss the impact of
advanced low-power low-voltage design methodologies of nanometer silicon
systems on test and reliability. Power and thermal issues, leakage, process
variations, susceptibility to environmental and operation-induced interference
drive the development of low-power, process-tolerant design techniques and
generate a new set of test and reliability challenges, questing for an
innovative set of methodologies and tools.
Download the programme for the workshop. (Published
Download the extended call for papers (pdf). The new
deadline is 21st March 2011.