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When: Wednesday, May 30th, 14h00-15h00
Title: Adaptive Testing: Conquering Process Variations
Organizer: Sule Ozev (ASU, USA)
Presenters: Sule Ozev (ASU, USA), Peter Maxwell (Aptina, USA), Ozgur Sinanoglu (NYU AD, EAU)
Increasing process variations result in increasing statistical diversity in manufactured devices. Test plans that are developed without this diversity in mind are bound to either over-test or under-test the devices or sometimes even both. Adaptive testing is a term that is generally used to tailor the test strategy to accommodate a wide range of variation in statistical characteristics of manufactured devices. In this tutorial, we will discuss many aspects of adaptive test for both digital and analog circuits and the challenges that we face moving forward, from data collection, to data processing, and equipment limitations. Our goal is to make the test community more aware of these efforts as well as start a discussion on the future of desired aspects of test and measurement equipment that help adaptive test become more applicable. Adaptive test is particularly useful when parametric measurements are needed. For instance, supply current or maximum frequency measurements in the digital domain, and pretty much any measurement in the analog domain, would qualify as parametric measurement. In light of this, we will first review adaptive test work in parametric measurements in the past decade or so, with emphasis on more recent work. These will include variance reduction techniques that have been employed for Iddq-based testing or min-Vdd measurements from the digital domain, and lot-to-lot or wafer-to-wafer test adaptation from the analog domain. We will then focus on recent test approaches for digital test techniques that are structural in nature, but rely on the speed of various paths in the circuit. We will discuss techniques that relate measurements from on-chip structures to the speed of the chip so as to minimize frequency searches, tailoring critical paths or path-based testing with respect to process variations. The last part of the tutorial will focus on challenges from an equipment, tool, and data flow perspective. In this section, we will discuss the limitations of the dataflow, how much dies can be traced, and how much processing can be done on-line on the tester. We will also discuss some of the useful capabilities desirable in test equipment that can make adaptive test easier and further reaching. Increasing process variations result in increasing statistical diversity in manufactured devices. Test plans that are developed without this diversity in mind are bound to either over-test or under-test the devices or sometimes even both. Adaptive testing is a term that is generally used to tailor the test strategy to accommodate a wide range of variation in statistical characteristics of manufactured devices. In this tutorial, we will discuss many aspects of adaptive test for both digital and analog circuits and the challenges that we face moving forward, from data collection, to data processing, and equipment limitations. Our goal is to make the test community more aware of these efforts as well as start a discussion on the future of desired aspects of test and measurement equipment that help adaptive test become more applicable. Adaptive test is particularly useful when parametric measurements are needed. For instance, supply current or maximum frequency measurements in the digital domain, and pretty much any measurement in the analog domain, would qualify as parametric measurement. In light of this, we will first review adaptive test work in parametric measurements in the past decade or so, with emphasis on more recent work. These will include variance reduction techniques that have been employed for Iddq-based testing or min-Vdd measurements from the digital domain, and lot-to-lot or wafer-to-wafer test adaptation from the analog domain. We will then focus on recent test approaches for digital test techniques that are structural in nature, but rely on the speed of various paths in the circuit. We will discuss techniques that relate measurements from on-chip structures to the speed of the chip so as to minimize frequency searches, tailoring critical paths or path-based testing with respect to process variations. The last part of the tutorial will focus on challenges from an equipment, tool, and data flow perspective. In this section, we will discuss the limitations of the dataflow, how much dies can be traced, and how much processing can be done on-line on the tester. We will also discuss some of the useful capabilities desirable in test equipment that can make adaptive test easier and further reaching.
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When: Wednesday, May 30th, 14h00-15h00
Title: Introduction to the Defect-Oriented Cell-Aware Test Methodology for significant reduction of DPPM rates
Organizer: Friedrich Hapke (Mentor Graphics, DE)
Presenter: Friedrich Hapke (Mentor Graphics, DE)
Physical defects like shorts and opens may occur during any step of the fabrication process. Well known fault models like stuck-at, transition N-detect, gate-exhaustive, embedded-multi-detect, timing-aware, and also layout-aware fault models on inter-connect lines etc. have proven to be insufficient for today's technologies that require very low defect (DPPM) rates. The root cause of this is, that state-of-the-art ATPG tools only assume faults on inputs and outputs of library cells and faults on inter-connect lines between library cells, but real cell-internal physical defects (like bridges and opens) within standard library cells are not targeted explicitly. This tutorial will give an introduction to a new defect-oriented test method called Cell-Aware. This new Cell-Aware method takes the layout of standard library cells into account when creating the new Cell-Aware ATPG library view. The tutorial will cover the whole Cell-Aware library characterization flow consisting of a layout extraction step, an analog fault simulation step of all cell internal bridges and opens and the cell-aware synthesis step to create the new Cell-Aware ATPG library views, which finally can be used in a normal chip design flow to generate production test patterns. These Cell-Aware production test patterns have a significantly higher quality than state-of-the-art patterns. The tutorial will also provide an introduction to the Cell-Aware ATPG algorithm. Cell-Aware characterization results from a 45nm library will be presented as well as pattern and coverage results from actual industrial designs. Finally production test results from several hundred thousand tested IC's are presented showing significant reduction of DPPM rates.
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