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Workshop on Low Power Design Impact on Test and Reliability (LPonTR)
The 5th IEEE International Workshop on Impact of Low Power Design on Test and Reliability (LPonTR) aims to bring together design, reliability and test engineers and researchers to discuss the impact of advanced low-power low-voltage design methodologies of nanometer silicon systems on test and reliability. Power and thermal issues, leakage, process variations, susceptibility to envi- ronmental and operation-induced interference drive the development of low-power, process-tolerant design techniques and generate a new set of test and reliability challenges, questing for an innovative set of methodologies and tools.

Download the Technical Program.

Key dates:
  • Submission deadline: 11th March, 2012
  • Notification of acceptance: 15th April, 2012
  • Final manuscript (electronic format): 14th May, 2012
  • Workshop: 31st May (4:00pm) - June 1st (4:00pm), 2012

    Workshop Highlights:
    Keynote Speakers:
    • Robin Wilson, STMicroelectronics, France
      Manufacturable Energy Efficient IC design "Taming the Untamed World"
    • Hans Manhaeve, Ridgetop Europe, Belgium
      Current testing for Low Power: Evil or Necessity ?!
    Invited Speakers:
    • Nikolaus Mittermaier, Synopsys, Germany
      Power Aware Test, a hot topic in Implementation and ATPG
    • Avinash Lingamneni, CSEM SA, Switzerland
      Realizing Energy-Parsimonious Systems through "Inexact" Circuits
    Special Sessions:
    • "Physical Design Methods and Test Solutions for 3D ICs" (organized and chaired by Aida Todri-Sanial, LIRMM, France)
      Speakers: Pascal Vivet (CEA-LETI, France), Vasilis Pavlidis (EPFL, Switzerland), Sylvian Kaiser (DOCEA Power, France)
    • "Cross-Layer Reliability and Low Power" (organized and chaired by Ilia Polian, Univ. of Passau, Germany)
      Speakers: Norbert Wehn (University of Kaiserslautern, Germany), Michael Nicolaidis (TIMA, France), Mehdi B. Tahoori (Karlsruhe Institute of Technology, Germany)
     

  • Workshop on Processor Verification, Test and Debug (IWPVTD)
    The key objective of this workshop, planned to be held in conjunction with the European Test Symposium, is to provide an informal forum for vigorous creative discussion and debate of Processor Verification, Test and Debug. The aim is to encourage the presentation and discussion of innovative ideas that may not yet have been fully developed for presentation at reviewed conferences to address these challenges. Additionally, the workshop invites embedded talks and tutorials on cutting edge topics related to processor test, verification, debug and reliability.

    This workshop has been canceled
     

    Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN)
    Constant advances in manufacturing yield and field reliability are important enabling factors for electronic devices pervading our lives, from medical to consumer electronics, from railways to the automotive and avionics scenarios. In the framework of the COST Action IC1103 - MEDIAN, (Manufacturable and Dependable Multicore Architectures at Nanoscale) this Workshop will provide an open forum for presentations in the above-mentioned fields.

    More details can be found here.

    Key dates:
  • Submission deadline: 15th March, 2012
  • Notification of acceptance : 15th April, 2012
  • Final manuscript (electronic format) : 30th April, 2012
  • Workshop: 31st May (4:00pm) - June 1st (4:00pm), 2012




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