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Keynote 1
When: Tuesday, May 29th
Title: Goldilocks Failures: Not Too Soft, Not Too Hard
Organizer: Sani Nassif (IBM, USA)
The semiconductor industry continues to push Silicon scaling for the next ten years since no viable alternative technology is sufficiently mature in that time frame. Simultaneously, the delay in crucial technologies like UV complicates further scaling by increasing cost and imposing ever larger tolerances that erode performance and density gains. The increasing levels of variability are creating new types of circuit failures which fall between the traditional "hard" and "soft" categories. This phenomena has been observed for some time in SRAM, but it is now seen in other sensitive circuits like latches. Studying this behavior leads to two important research opportunities: bridging the gap between performance prediction and test, as well as preparing the CAD and Test communities for future post-CMOS technologies.


Keynote 2
When: Wednesday, May 30th
Title: 3D Chip Stacking: The Sky Is The Limit
Organizer: Erik Jan Marinissen (IMEC,BE)
Over its history, semiconductor design and technology has been creeping up in the z-direction in order to cramp ever more functionality in a small chip package. The number of stacked metal layers has increased drastically to give way to growing on-chip interconnect needs. With FinFETs, transistors are expanding in height to increase performance at smaller dimensions. With Package-on-Package (PoP) and System-in-Package (SiP), we have been exploiting the third dimension to minimize footprint, which enables our handheld mobile gadgets. And now, with the advent of micro-bump and through-silicon via (TSV) technologies, a new boost is given to the mind-boggling high-performance/low-power achievements of the semiconductor industry. Confident that we will resolve the numerous technical challenges still ahead, a Valhalla of new architecture, design, test, manufacturing, and business opportunities still lies ahead of us, where the sky is truly the limit...


Invited Presentation
When: Tuesday, May 29th
Title: Power-Aware Testing: The Next Stage
Organizer: Xiaoqing Wen (Kyushu Institute of Technology, Japan)
Advances in hardware/software-based power management are dramatically driving down functional power dissipation; however, they are also widening the gap between functional and test power, resulting in test-power-induced yield loss for VLSI circuits usually designed capable of handling only functional power. Although numerous power-aware test techniques have been proposed in the past decade for reducing test power, testing for power management circuitry, and streamlining power management in the complete design-and-test flow, many of them suffer from unguaranteed test power safety, inflated test data, increased test time, nonnegligible area overhead, compromised test quality, or even performance degradation. These problems make it necessary to move power-aware testing to the next stage, in which the focus should evolve from indiscriminate test power reduction to guaranteed test power safety. This presentation will highlight the needs for this important change of focus and identify major characteristics required for the next stage of research and development in power-aware testing.





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