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When: Tuesday, May 29th, 17.00 to 18.30
Title: VLSI Test Technology: Why is the field not sexy enough?
Organizers: Said Hamdioui (TU Delft, The Netherlands), Rob Aitken (ARM USA)
Panelists: From Industry:
  • Bram Kruseman (NXP, The Netherlands)
  • Piet Engelke (Infineon, Germany)
  • Yervant Zorian (Synopsys, USA)
  • Bob Madge (Global Foundries)
    From Academia:
  • Hans-Joachim Wunderlich (Uni. Stuttgart, Germany)
  • Subhasish Mitra (Stanford Uni, USA)
  • Zebo Peng (Linkoping Uni, Sweden)
  • Xiaowei Li (CAS, China)
  • Although it is an integral part of any manufactured chip and a crucial step to guarantee the required quality, VLSI Test technology seems to become less attractive/interesting for the research community. Funding bodies are minimizing their funding in the area, scientists are moving to other hot topics, industry is not seriously supporting academia in the field, etc. The panel session aims at gathering opinions -both from industry and academia- on the above trends and discuss some strategic options to promote the field of VLSI test technology. Are there any challenges that Industry is expecting from academia to work on? Is academia doing what industry is expecting? What are the expectations of the industry and those of academia? How to optimize the collaboration and make it effective and productive? Does the lack/poor industrial financial support for academia mean that there are no interesting topics to work on? Etc. These and other related questions will be addressed by a group of experts with different backgrounds.
    FINE; $p2=<<
    When: Thursday, May 31st, 11.00 to 12.30
    Title: The impact of functional safety standards in the design and test of reliable and available integrated circuits.
    Organizer: Riccardo Mariani (YOGITECH SpA, Italy)
    Panelists:
  • Pascal Chaumette (BWI Group)
  • Frank Reichenbach (ABB Corporate Research Norway)
  • Petr Sladecek (STMicroelectronics)
  • Pete Harrod (ARM)
  • Victor Reyes (Synopsys)
  • Hari Pendurty (Texas Instruments)
  • Nowadays, very complex hardware components are largely used in safety-critical domains such as automotive, aerospace, medical, industrial and railway. Besides systematic failures and misuse, the root causes of HW functional failures are defects, flaws (defects whose presence does not interfere with normal operation during manufacturing test, but which cause life failure) and random faults (permanent, intermittent and transient faults caused by random events during operation). To handle this complexity, functional safety standards like IEC 61508 and ISO 26262 are giving requirements, evaluation metrics and methodologies to define "how much safe" or "how much available" shall be a given component or system. As a consequence of that, the design and test of reliable and available integrated circuits requires a specific approach impacting both digital and analogue HW; moreover, safety-oriented methodologies shall be available to drive the specifications and verify the implementation. The panel will give an update on latest requirements and HW fault models of ISO 26262 (the international norm ruling functional safety for automotive) and IEC 61508 2nd edition (an international norm widely used in industrial domain). Moreover, the panel will compare the different perspectives on that topic from an automotive Tier1, an industrial system manufacturer, two silicon vendors involved in automotive and industrial markets, an IP provider and an EDA vendor, introducing their experiences and expectations to the testing community.
    FINE; $p3=<< When: Thursday, May 31st, 11.00 to 12.30 Title: Re-using Chip Level DFT at Board Level Organizers: Xinli Gu (Huawei), Krishnendu Chakrabarty (Duke University), Erik Larsson (Lund University) Moderator: Artur Jutman (Testonica) Panelists:
  • Jeff Rearick (AMD)
  • Bill Eklow (Cisco)
  • Martin Keim (Mentor Graphics)
  • Jun Qian (AMD) As chips are getting increasingly complex, there is no surprise to find more and more built-in DFX. This built-in DFT is obviously beneficial for chip/silicon DFX engineers; however, board/system level DFX engineers often have limited access to the build in DFX features. There is currently an increasing demand from board/system level DFX engineers to reuse chip/silicon DFX at board/system level. This special session will discuss: What chip access is needed for board-level for test and diagnosis? How to accomplish the access? Will IEEE P1687 and IEEE 1149.1 solve these problems? FINE; ?>

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