TUTORIALS

MAY 26th, 1998 

A Title: Embedded Core-based System-on-Chip Test
  Presenter: Yervant Zorian (LogicVision Inc., USA)
  Summary: This tutorial will address the challenges and current industrial practices in the design, validation, and test of systems-on-a-chip, which is going to dominate the system design methodology by year 2000. A major key to the success of the new system design methodology lies in the development and use of pre-designed, pre-characterized, and pre-verified functional blocks called cores. A wide range of industrially available cores, including processor, microcontroller, DSP, interface, multimedia, and communications/networking cores will be described. System-on-a-chip design methodologies using cores will be described, including required software and hardware development support, and issues in system-level integration. Validation methodologies currently used to verify the correctness of such systems will be described. The tutorial will focus on the test related aspects of system-on-chip containing embedded cores. Also discused will be the testing requirements for such systems, the test access mechanisms to each core and the standardization requirements, the needs and the techniques to apply controllability and observability to the embedded unit boundaries in order to provide effective isolation for testing. The isues of debugging and diagnosing embedded units will be analyzed. The tutorial the will cover the state-of-the-art practices in testability schemes for embedded cores and the porting of test data. Finally, recent challenges and adopted strategies to implement an integrated test strategy from embedded cores to a system-on-a-chip will be discussed.
Biography: Yervant Zorian is the chief technology advisor for Logic Vision, Inc., in San Jose, California. He has recently become editor-in-chief of IEEE Design & Test, after serving for four years as associate editor-in-chief. He also chairs the IEEE Computer Society Test Technology Technical Committee. Zorian received an MS degree in computer engineering from the University of Southern California and a PhD in electrical engineering from McGill University in Canada. He is a member of the IEEE and the Computer Society.
Location: HOTEL CALIPOLIS (ETW98 Venue)
Schedule: 9:00 to 17:00 (with two coffe breaks and one lunch included)

 

B Title: Why Field Returns: Defect-Based Analysis of Test Escapes and Reliability Failure Mechanisms
  Presenter: Chuck Hawkins (University of New Mexico and Sandia National Labs, USA)
  Summary: CMOS IC Test and Reliability Engineering share responsibility for field returns although these two fields seldom communicate with each other. This tutorial analyzes test escapes from a defect based approach relating defect electrical behavior to different test method sensitivities.  The commonality of reliability and test related defects are emphasized. The major IC reliability failure mechanisms are metal voiding and hillock formation, oxide wearout, rupture, hot carrier damage, corrosion, and ESD/EOS. Each of these failure mechanisms is described with perspective on their severity. Finally, the reliability link to test the burn-in process is described with emphasis on burn-in elimination studies.
Biography: Chuck Hawkins is a Professor in the EECE Dept. at the University of New Mexico, Alburquerque, New Mexico. He teaches the electronics subjects of design, test, reliability, and failure analysis. He also teaches short courses in these disciplines. His research work is done in collaboration with Sandia National Labs where he has been associated since 1984. He did a sabbatical in 1997 with a Q&R Dept. at Intel Corp. He has co-authored two books in electronics, the last being on IDDQ Testing with Kluwer Publishers. He was General Chair of the 1996 Test Conference and was Program Chair at 1993. He has won several Best Paper awards in CMOS test with co-workers. He spent 8 weeks in the summer of 1997 with the EE Dept. at the Technical University at Delft and will do a similar visit with the EE Dept. at the Universitat de Illes Balearic in Mallorca in 1998.
Location: HOTEL CALIPOLIS (ETW98 venue)
Schedule: 9:00 to 17:00 (with two coffe breaks and one lunch included)

 

 

HOME PAGE

WELCOME
CONFERENCE COMMITTES
VENUE AND HOTEL
PROGRAM
GUIDELINES FOR POSTER PREPARATION
SOCIAL PROGRAM
ADVANCE REGISTRATION
HOTEL RESERVATION
GENERAL INFORMATION
INFORMATION ABOUT SITGES
INFORMATION ABOUT BARCELONA
BARCELONA FROM THE AIR