IEEE European Test Workshop, May 25-28, 1999

Steigenberger Inselhotel, Constance, Germany

Home to ETW99



During the last week of May (May 25 - 28, 1999) we host the European Test Workshop in Constance, nearby the Blackwood Forest and the Alps of Switzerland and Austria.
This workshop is a well recognized forum for presenting and discussing trends and hot topics in the area of circuit and system testing. The ETW is the only event in Europe focused on test research and development and has a reputation of high quality which makes it very attractive for active professionals working in research institutes, universities, and industries in the field of testing. Recent years showed the strong confidence of the community in the ETW as a place for discussion, exchange of ideas as well as a good occasion for initiating or strengthening fruitful personal relationships.
On behalf of the Organizing and Program Committees we would like to invite you to participate in the ETW'99. We are sure that the effort to attend will be rewarded by motivating technical and personal interactions with your colleagues in a friendly and constructive atmosphere.
We are looking forward to welcoming you in Constance
H.-J. WunderlichC. Landrault
ETW'99 General ChairETW'99 Program Chair


TUESDAY, MAY 25, 1999
9:00 am - 5:00 pm TTTC TUTORIALS
Chair: Sybille Hellebrand (University of Stuttgart)
The TTTC Tutorials Group offers 2 full day tutorials in state-of-the-art topics in test through the Test Technology Educational Program. This provides opportunities for design and test professionals to update their knowledge-base in test, and earn official accreditation from TTTC. Topics are:
A) Solving the test problems of nanometer technologies: a status update and
B) Testing Embedded-Core Based System Chips.
Attendance to tutorials requires a special fee.

8:30 - 10:00 am OPENING (Festsaal)
Welcome. Hans-Joachim Wunderlich, General Chair (U of Stuttgart)
Program Introduction. Christian Landrault, Program Chair (LIRM Montpellier)
The role of the IEEE Test Technology Technical Council. Yervant Zorian, TTTC Chair (LogicVision, USA)
Keynote Address: "The Currents of Change: Navigating on Rivers with Decreasing Channels" Peter Maxwell (Hewlett-Packard, Palo Alto, USA)
Abstract: Current-based testing is undergoing a period of re-evaluation. Navigating and successfully avoiding defects on the River of Chips has become extremely hazardous due to the Deep Submicron Rapids, where the gentle currents become raging turbulences, rendering all but useless the traditional techniques. This talk takes a historical perspective of IDDQ, as the major current-based testing approach. Successes and not-so-successes are highlighted, before exploring newer developments which offer ways of extending the technique. One question addressed is whether other current-based techniques such as dynamic IDD or thermal testing will be required to have any kind of current-based testing which will be effective in the future.
10:00 - 11:00 am POSTER SESSION P1
Posters & Coffee
Abstract: Improved TPGs, a data path BIST scheme, concurrent checking, output compaction, hierarchical TPG and BIST for systems with distributed memories are addressed.
Posters: "Design of a Test Pattern Generator Using a New LFSR with D and T Flip-Flops", T. Garbolino, A. Hlawiczka (Silesian TU of Gliwice, P)
"Random-Pattern Coverage Enhancement for BIST", O. Novak (TU Liberec, CZ)
"Datapath BIST Scheme for Full Testing", D. Berthelot, M.L. Flottes, B. Rouzeyre (LIRM Montpellier, F)
"Self-dual Sequential Circuits for Concurrent Checking", A. Dmitriev, V.V. Saposhnikov, Vl.V. Saposhnikov, M. Goessel ( Railway Transportation State U, RUS; U of Potsdam, D;)
"Two-Output Space Compactor and Multi-Input Shift Register with Zero Output for BIST", K. Gucwa, A. Hlawiczka (Silesian TU of Gliwice, PL)
"STAR-DUST: Hierarchical Test of Embedded Processors by Self-Test Programs", P. Marwedel, U. Bieker, M. Kaibel, W. Geisselhardt (U of Dortmund, D; U of Duisburg)
"A Low-Cost Reusable BIST Processor for RAMs", A. Benso, S. Chiusano, M. Lobetti Bodoni, P. Prinetto (Politecnico di Torino, I; ITALTEL, I)
11:00 am - 12:30 pm SESSIONS 1A and 1B
Session 1A (Festsaal)
Title: BIST: From Basics to Applications
Abstract: The session deals with BIST at different levels of abstraction. A tool is presented for BIST insertion in hierarchical systems. Next, a method is presented for computing the most effective initial state of a test register at gate level. Finally, as a case study, a cryptographic coprocessor is made self-testable.
Papers: "A High-level EDA Environment for the Automatic Insertion of HD-BIST Structures", A. Benso, S. Cataldo, S. Chiusano, P. Prinetto, Y. Zorian (Politecnico di Torino, I; LogicVision Inc., USA)
"On Calculating Efficient LFSR Seeds for Built-In Self Test", C. Fagot, O. Gascuel, P. Girard, C. Landrault (LIRM Montpellier, F)
"On Random Pattern Testability of Cryptographic VLSI Cores", A. Schubert, W. Anheier (U of Bremen, D)
Session 1B (Blauer Salon)
Title: Functional and Structural Testing of Analog Circuits
Abstract: The usual practice in analog testing is based on verifying the functionality of the circuit by verification of some design specifications. An alternative approach used for digital circuits is based on targeting possible defects. This session investigates these two alternatives. The first paper describes a defect oriented testing approach, the last paper a specification oriented testing approach. The second paper presents a solution mixing both approaches.
Papers: "Functional and Structural Testing of Switched-Current Circuits", M. Renovell, F. Azaïs, J.-C. Bodin, Y. Bertrand (LIRM Montpellier, F)
"Practical Implementation of Defect-Oriented Testing for a Mixed-Signal Class-D Amplifier", R.H. Beurze, Y. Xing, R.J.W.T. Tangelder, N. Engin, R. van Kleef (U of Twente, NL; Philips Semiconductors, NL)
"A New Approach for Nonlinearity Test of ADCs/DACs and Its Application in BIST", F. Xu (U of Hanover, D)
12:30 - 2:00 pmLUNCH
2:00 - 3:30 pm SESSIONS 2A and 2B
Session 2A (Festsaal)
Title:IDDx Testing
Abstract: IDDq test vector compaction, on-chip IDDt current monitors and off-chip IDDx monitors are described, as well as their usefulness for digital and analog test.
Papers: "Compaction of IDDQ Test Sequence Using Reassignment Method", T. Maeda, K. Kinoshita (Osaka U, J)
"Experimental Results on BIC Sensors for Transient Current Testing", R. Picos, M. Roca, E. Isern, J. Segura (U of the Balearic Islands, Palma de Mallorca, E)
"Application of Supply Current Testing to Analogue Circuits, Towards a Structural Analogue Test Methodology?!", H. Manhaeve, J. Verfaillie, B. Straka, J.P. Cornil (KHBO-IMEC Oostende, B; Alcatel, B; CEDO Brno, CZ)
Session 2B (Blauer Salon)
Title:Industrial Experiences and Challenges (I)
Abstract: This series of sessions deals with hot topics from industrial practice. Case studies, solutions for recent problems, new tools and trends will be discussed. Usually, for these most current presentations no formal papers will be available in order to keep confidentiality and timeliness. They are of interest in order to learn from industrial colleagues or in order to get recent material for research topics.
Papers: "An Economic Driven Test Strategy Selection for a Mixed VLSI Circuit Using swBIST Solutions", D. Appello, S. Audrain, E. Chioffi, A. Daolio, F. Di Giovanni (STMicroelectronics, I)
"Challenges in DfT and production testing of advanced boards", Monica Lobetti Bodoni (Italtel SpA)
"A new Method for SDRAM testing in systems and boards: SCITT", Frans de Jong (Philips ED&T, Eindhoven, NL)
3:30 - 4:30 pm POSTER SESSION P2
Posters & Tea
Title:High Level Testability and Current Testing
Abstract: This session deals with test cost economics, current monitors and test pattern generation for current testing, testability enhancement techniques and test generation for hard-software codesign.
Posters: "Cost Analysis Linking Design, Test & Maintenance", T. Riedel, M.G. Wahl, A.P. Ambler, (U of Siegen, D; U of Texas at Austin, USA)
"ATPG for Transient Current Testing", E. Isern, M. Roca, J. Segura (U of the Balearic Islands, Palma de Mallorca, E)
"A Behavioral-Level Testability Enhancement Technique", E. Larsson, Z. Peng (Linköping U, S)
"A Uniform Test Generation Technique for Hardware/Software Systems", G. Jervan, P. Eles, Z. Peng (Linköping U, S)
"Testability Analysis and Cost/Quality Trade-off in Synthesis for Testability", P. Bukovjan, M. Marzouki, W. Maroufi, V. Drabek (LIP6/ASIM Laboratory, Paris, F)
4:30 - 5:30 pmSESSIONS 3A and 3B
Session 3A (Festsaal)
Title:Testing MEMs and Switched Capacitors
Abstract: This session deals with the diagnosis of faults in switched capacitor circuits, and the detection of faults in MEMs as well as the development of test strategies for MEMs based designs.
Papers: "A DFT for Semi-DC Fault Diagnosis for Switched-Capacitor Circuits", S.-J. Kuo, C.L. Lee, S.-J. Chang, J.E. Chen (National Chiao Tung U, Hsin-Chu, RC; Chung-Hua U, Hsin-Chu, RC)
"Extending Fault-Based Testing to Microelectromechanical Systems", Salvador Mir, B. Charlot, B. Courtois (TIMA Laboratory, Grenoble, F)
Session 3B (Blauer Salon)
Title:Industrial Experiences and Challenges (II)
Paper: "Design of a Test Simulation Environment for Test Program Development", J.J.O. Riordan (Analog Devices, IRL)
"ATE Test Solutions for System on Chip", Michael Stichlmair (Advantest Europe, München, D)
5:30 - 8:30 pmWALKING TOUR & DINNER
8:30 - 10:00 pmEVENING BREAKOUT SESSION (Festsaal)
Participants will be asked to join one of the "breakout groups", to brainstorm, in a lively and relaxing atmosphere, properly supported by good wine, on one of the following hot topics:
  • Digital parts to support Analog and RF testing, and Analog BIST, Peter Maxwell (Hewlett-Packard, USA)
  • The future of Iddq and delay tests in nanometer technologies, Tom Williams (Synopsys, USA)
  • Splitting test functions between BIST and External test, (LogicVision, USA
  • How much can dependability rely on On-line test and Built-In self repair? Michael Nicolaidis (TIMA, France)

THURSDAY, MAY 27, 1999
7:30 - 8:20 amFRINGE MEETING
"SEMI International Standards Program Information & Update Session"
The purpose of this session is to present the "SEMI International Standards Program" and an "Update on the current activities in the area of Test". SEMI will provide a breakfast buffet to the attendees.
8:30 - 10:00 amSESSIONS 4A and 4B
Session 4A (Festsaal)
Title:ATPG and Fault Modeling
Abstract: In this session the first two papers present techniques to speed up ATPG by exploiting high level information and by heuristics to avoid test generation for redundant faults. The third paper analyzes the adequacy of commonly used fault models for bridging faults.
Papers: "High-Level Path Activation Technique to Speed Up Sequential Circuit Test Generation", J. Raik, R. Ubar (Tallinn TU, EST)
"On Avoiding Undetectable Faults During Test Generation", I. Pomeranz, S.M. Reddy (U of Iowa, USA)
"Some Fundamental Limitations of the Composite Stuck-at Model to Model Bridge Behaviour", S. Chakravarty (Intel Corp., USA)
Session 4B (Blauer Salon)
Title:Industrial Experiences and Challenges (III)
Papers: "Challenges in testing high density ASICs", Maurizio SPADARI (LSI Logic)
"Delay Fault Testing for Via Defects and Other Opens", Guido Gronthoud, Keith Baker, Maurice Lousberg (Philips ED&T, Eindhoven, NL), Frank Poehl (Philips Semiconductors, Hamburg, D), Chuck Hawkins (University of New Mexico, Albuquerque, NM, USA)
"Debug Facilities in the TriMedia CPU64 Architecture", Harald Vranken (Philips Research, Eindhoven, NL)
10:00 - 11:00 amPOSTER SESSION P3
Posters & Coffee
Title:Digital ATPG and Analog Testing
Abstract: In this poster session test pattern generation for delay faults, embedded cores and FPGAs, as well as defect oriented approaches for analog circuits are addressed.
Posters: "ATPG Using Fast Justification and Propagation on the Implication Graph", P. Tafertshofer, A., Ganz (TU of Munich, D)
"Using a Software Test Method for Testing Programmable Devices in Hardware/Software Systems", O.-E.-K. Benkahla, A. Chauché, C. Aktouf, C. Robach (LCSI-INPG, Valence, F)
"The Practical Use of a Defect-Oriented Approach in Mixed-Signal Testing", N. Engin, H.G. Kerkhoff (U of Twente, NL)
"Test-Pattern Generation and Fault Coverage Determination of Embedded Cores", V.A. Zivkovic, R.J.W.T. Tangelder, H.G. Kerkhoff (U of Twente, NL)
"Layout-based Defect Analysis and Test of Radiation Hardened Integrated Mixed-Signal Circuits", D. De Venuto, M.J. Ohletz, F. Corsi (Alcatel Microelectronics, B; Università di Lecce, I; Politecnico di Bari, I)
"The Application of neuMOS Transistors to Enhanced Built-in Self-Test (BIST) and Product Quality", R. Nicholson, A. Richardson (Lancaster U, GB)
"Gate Delay Test Generation for Industrial Circuits Considering Embedded Cores", F. Pöhl, V. Meyer, W. Anheier (U of Bremen, D)
11:00 - 11:30 amREPORT ON BREAKOUT SESSION (Festsaal)
11:30 am - 12:00 pmIndustrial Experiences and Challenges (IV) (Festsaal)
Paper: "Test Experiences from an IP Provider", Peter Harrod (ARM Ltd., UK)
12:00 - 1:30 pmLUNCH
1:30 -3:00 pmSESSIONS 5A and 5B
Session 5A (Festsaal)
Title: BIST for Sequential Circuits and Delay Faults
Abstract: The first paper presents a BIST scheme for delay testing which allows to trade-of between hardware overhead and test time. The second and the third paper present techniques to facilitate the BIST of sequential circuits targeting pseudo-random and deterministic test.
Papers: "A Scalable BIST Architecture for Delay Faults", M. Keim, I. Polian, H. Hengster, B. Becker (U of Freiburg, D)
"Partial Set for Flip-Flops Based on State Requirement for Non-scan BIST Scheme", M.-L. Flottes, C. Landrault, A. Petitqueux (LIRM Montpellier, F)
"Deterministic BIST with Partial Scan", G. Kiefer, H.-J. Wunderlich (U of Stuttgart, D)
Session 5B (Blauer Salon)
Title: Fault Simulation and Fault Coverage of Analog Circuits
Abstract: The first paper in this session targets the relation between possible numerical problems and their impact on analog fault simulation and decision making. The second paper deals with statistical approaches to reduce the fault simulation effort for analog circuits taking into account parameter variations. The third paper focuses on a method to improve the testability of structural and parametric faults in analog circuits.
Papers: "On the Fault-Injection-Caused Increase of the DAE-Index in Analogue Fault Simulation", B. Straube, K. Reinschke, W. Vermeiren, K. Röbenack, B. Müller, C. Clauß (Fraunhofer IIS/EAS Dresden, D; Dresden U of Technology,D)
"Analog Fault Simulation and Test Optimization under Parameter Variations", A. Khouas, A. Derieux (Université Pierre et Marie Curie, ASIM/LIP6, Paris, F)
"On Maximizing the Coverage of Catastrophic and Parametric Faults", A.M. Brosa, J. Figueras (UPC, Barcelona, E)
3:00 -11:00 pmSOCIAL EVENT

FRIDAY, MAY 28, 1999
8:30 - 10:00 amSESSIONS 6A and 6B
Session 6A (Festsaal)
Title:From System Level to Defect Oriented Test
Abstract: Boundary Scan Test for SOBs prototype debug and validation is described. Moreover, challenges in SOC testing, namely how functional test can be reused to increase the defect coverage of embedded cores, are addressed.
Papers: "Using the BS register for capturing and storing n-bit sequences in real-time", G.R. Alves, J.M. Martins Ferreira (ISEP, Porto, P)
"From System Level to Defect-Oriented Test: a Case Study", O.P. Dias, J. Semião, M.B. Santos, I.M. Teixeira, J.P. Teixeira (INESC, Lisboa, P, INESC, Setubà, P; INESC, Algarve, P)
"Cost Effective Testing of Systems on Silicon Areas for Optimization", P. Muhmenthaler (Siemens AG, D)
Session 6B (Blauer Salon)
Title:Industrial Experiences and Challenges (V)
Papers: "PPM - A Crisis or a Challenge", Graeme Francis (Philips Semiconductors Southampton)
"DRAM Test Callenges", W. Daehn (Infineon Technologies AG, München, D)
"Recent experiences with embedded ATE in System-on-Chips", Y. Zorian (LogicVision, San Jose Ca. USA)
10:00 - 11:00 amPOSTER SESSION P4
Posters & Coffee
Title:DFT and Dependability
Abstract: Poster session P4 presents a number of interesting approaches for DFT on system, behavioral, and RT level. Furthermore, a test structure for asynchronous pipelines is proposed. It is also shown how traditional techniques like boundary scan can be exploited to increase the dependability of systems.
Posters: "A DFT Method for RTL Data Paths Achieving 100% Fault Efficiency under Hierarchical Test Environment", H. Wada, T. Masuzawa, K.K. Saluja, H. Fujiwara (Nara Institute of Science and Technology, J; U of Wisconsin-Madison, USA)
"A Novel Ad Hoc Test Structure for Asynchronous Pipeline Circuits", Y.L. Ling, C.C.S. Oliver, C.C. Fat (The Chinese U of Hong Kong, RC)
"High-Level Design-For-Testability of Complex Designs", H. Fleury, C.Aktouf, C. Robach (LCIS-ESISAR, Valence, F)
"Partial Scan Methodology for RTL Designs", Z. Kotasek, F. Zboril, J. Hlavicka (TU of Brno, CZ; Czech TU, Prague, CZ)
"DFT for Delay-Fault Diagnosis in Digital High-Speed ICs", H.G. Kerkhoff, K. van Nee, H. Speek (U of Twente, NL)
"Possibilities and Limitations of Self-Test and Functional Backup for Standard Processor Cores in Embedded Applications", M. Pflanz, H.T. Vierhaus (TU of Brandenburg at Cottbus, D)
"Adding Fast Parity Check to BST for Concurrent Monitoring", J.M.V. Santos, J.M.M. Ferreira (ISEP, Porto, P, FEUP, Porto, P)
"0.35um CMOS 1.5-V Current Sensor", I. Pecuh, M. Margala, V. Stopjakova (U of Alberta, CDN; Slovak TU, Bratislva, SK)
11:00 am - 12:30 pmSESSIONS 7A and 7B
Session 7A (Festsaal)
Title: Testing FPGAs and Regular Arrays
"Abstract: This session addresses the problem of testing particular regular structures, such as SRAM-based FPGAs and DRAMs. The first paper proposes an approach to minimize the number of test configurations for a SRAM-based FPGA. The second paper proposes a modification of the FPGA architecture to accelerate the process of configuration loading. The third paper studies the problem of cross-talk in DRAMs implemented in deep submicron technology.
Papers: "Test Configuration Minimization for the Logic Cells of SRAM-Based FPGAs: A Case Study," M. Renovell, J.M. Portal, J. Figueras, Y. Zorian (LIRM Montpellier, F; UPC, Barcelona, E; LogicVision Inc., USA)
"Design of an Automatic Testing for FPGAs", A. Doumar, T. Ohmameuda, H. Ito (Chiba U, J)
"Crosstalk and DRAMs"; Z. Yang, S. Mourad (S3 Inc., USA, Santa Clara U, USA)
Session 7B (Blauer Salon)
Title: Industrial Experiences and Challenges (VI)
Papers: "Pulsar: A versatile multipurpose data acquisition and generation system", V. Himpe (Alcatel Microelectronics, B)
"Challenges in test re-use from system to die test", Silvano Motto (CAEN Microelettronica)
"Towards a Roadmap on Test in Europe", Rene Segers (Philips Semiconductors, Eindhoven, NL)
"The Role of Test Protocols in Testing of Embedded-Core Based System ICs", Erik Jan Marinissen, Maurice Lousberg (Philips Research, Eindhoven, NL; Philips Electronic Design & Tools, Eindhoven, NL)
12:30 - 2:00 pmLUNCH
2:00 - 3:30 pmSESSION 8 (Festsaal)
Title:Low Power Testing
Abstract: Session 8 deals with the problem of power reduction in pseudo-random BIST. The first paper concentrates on scan-based BIST while the remaining two present solutions for test-per-clock BIST.
Papers: "An Approach to Reduce the Power Consumption during Scan-Based BIST", S. Gerstendörfer, H.-J. Wunderlich (U of Stuttgart, D)
"A New BIST Architecture for Low Power Circuits", F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante (Politecnico di Torino, I)
"Low Power BIST by Filtering Non-Detecting Vectors", S. Manich, A. Gabarrò, J. Figueras,P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, P. Teixeira, M. Santos (UPC, Barcelona, E; LIRM Montpellier, F; INESC, Lisboa, P)
3:30 - 3:45 pmETW 2000
Joao Paolo Teixeira, General Chair ETW'00, (INESC, Lisboa, P) Paolo Prinetto, Program Chair ETW'00, (Politecnico di Torino, I)
3:45 - 4:00 pmCLOSING
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