IEEE European Test Workshop, May 25-28, 1999

Steigenberger Inselhotel, Constance, Germany

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TUESDAY, MAY 25, 1999
9:00 am - 5:00 pm TTTC TUTORIALS
Chair: Sybille Hellebrand (University of Stuttgart)
The TTTC Tutorials Group offers 2 full day tutorials in state-of-the-art topics in test through the Test Technology Educational Program. This provides opportunities for design and test professionals to update their knowledge-base in test, and earn official accreditation from TTTC. Topics are:
A) Solving the test problems of nanometer technologies: a status update and
B) Testing Embedded-Core Based System Chips.
Attendance to tutorials requires a special fee.

Tutorial A Solving the test problems of nanometer technologies: a status update.
Speakers: Sandip Kundu (Test Technology Group)
Sreejit Chakravarty (Intel Corporation, Santa Clara, USA)
Duration: 6 hours (from 9:00 to 17:00)
Summary: Analysis of available data show that the advent of nanometer technology has brought with it several test challenges in the domains of exposing permanent defects, accelerating aging defects and exploring the range of soft failures.
The difficulties are further aggravated by the need to assure good DPM without adversely affecting yield. In addition, future test solutions must tackle with the ever increasing size of designs to be targeted, the changing nature of the predominant failure mechanisms and lagging Automatic Test Equipment (ATE) technology.
This tutorial is aimed at educating the participants in the test challenges posed by nanometer technologies and present ideas on how to tackle them. More specifically we will discuss problems and solutions to these problems in the areas of delay test, speed binning, IDDQ test and ideas on tackling cross-talk and noise induced faults.
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Tutorial B Testing Embedded-Core Based System Chips.
Speakers: Erik Jan Marinissen (Philips Research, Eindhoven, NL)
Yervant Zorian (LogicVision, San Jose Ca. USA)
Duration: 6 hours (from 9:00 to 17:00)
Summary: Advances in semiconductor process and design technology enable the design of complex systems-on-chips. Traditional IC design, in which every circuit is designed from scratch and reuse is limited to standard-cell libraries, is more and more replaced by a design style based on embedded large reusable modules, the so-called cores. This core-based design style poses a series of new challenges, especially in the test domain. Therefore, testing of embedded cores is one of the current Hot Topics in the international test community.
This tutorial provides an introduction into core-based design and test, and an overview of current academic and industrial practices in core test. The current status of industry-wide efforts and standardization in VSIA and IEEE P1500 is discussed. The main modules of the tutorial are
  1. Challenges in Embedded-Core Test,
  2. Conceptual Architecture for Core Test Access,
  3. Industry-Wide Efforts,
  4. SOC Test Tools & Flows, and
  5. Industrial Experiences.
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