| 07:30-08:30 |
Symposium
Registration |
| 08:30-10:00 |
Session 1: Opening Session
(Plenary) |
| 08:30-08:50 |
Opening remarks |
| 08:50-09:25 |
Keynote address |
| |
The growing Importance of Package Technology
and Related Test Challenges |
| |
R. SCHEUENPFLUG, Vice President Assembly &
Interconnect Technology (Infineon - Germany) |
| 09:25-10:00 |
Invited Talk |
| |
Trends in BIST and Dignosis |
| |
H.J. WUNDERLICH, Professor (Universität Stuttgart
- Germany) |
|
| 10:00-11:00 |
Poster Session 1 |
| P1.1 |
On the development of a Low-cost
Diagnostic Flow for Efficient Failure Analysis
D. MARTIN, G. HALLER (ST Microelectronics - France),
F. AZAIS, P. NOUET (LIRMM - CNRS/Univ Montpellier 2 - France) |
| P1.2 |
An Automated TEM-Cell Measurement Environment
to Simplify the Characterization of the Radiated Electromagnetic Emission
of Ics
A. TANDA, T. OSTERMANN (University of Linz - Austria) |
| P1.3 |
Test Set Compaction and Compression for Circuits with Scan
O. NOVAK, J. ZAHRADKA, M. HOLUBEC, J. JENICEK (TU Liberec - Czech
Republic) |
| P1.4 |
Efficient Test Delivery in Decoder Driven Scan Architectures
A. ORAILOGLU, B. ARSLAN (University of California at San Diego
- USA) |
| P1.5 |
Test Instruction Set (TIS): An Instruction Level CPU Core
Self-Testing Method
S. SHAMSHIRI, H. ESMAEILZADEH, M. ZLISAFAEE, P. LOTFIKAMRAN,
Z. NAVABI (University of Tehran - Iran) |
| P1.6 |
Targeting Conditional Operations in Sequential Test Pattern
Generation
J. RAIK, R. UBAR (Tallinn Technical University - Estonia) |
|
| 11:00-12:30 |
Session 2 |
| 11:00-12:30 |
Session 2.a: Debug and Diagnosis |
| Moderator: H. FUJIWARA, Nara Institute
of Science and Technology - Japan, M. NICOLAIDIS, IROC Technologies
- France |
| I2.a.1 |
Test patterns for better Scan Chain
Diagnosis in industrial test flow
L. VALENCIA (ST Microelectronics - France) |
| I2.a.2 |
A BIST-based Broken Scan Chain Diagnostics
P. SONG (IBM T. J. Watson Research Center - USA), W. HURLEY, O.
FORLENZA, F. MOTIKA (IBM System and Technology Group - USA) |
| F2.a.3 |
At-Speed On-Chip Diagnosis of Board-Level Interconnect
Faults
A. JUTMAN (Tallinn Technical University - Estonia) |
| |
|
| 11:00-12:30 |
Session 2.b: Analog Measurement Techniques |
| Moderator: P.CAUVET, Philips, A. PATARICZA,
Tech. Univ. of Budapest - Hungary |
| F2.b.1 |
Accurate Tap-Delay Measurements Using a Differential
Oscillation Technique
O. PETRE, H. KERKHOFF(University of Twente - The Netherlands) |
| I2.b.2 |
Arbitrary Waveform RF Noise Source for Production
Noise Figure Measurements
J. KELLY, M. KARA, T. HEISTAND, F. GOH (Agilent Technologies -
USA) |
| F2.b.3 |
Delay Chain Based Programmable Jitter Generator
T. XIA (UVM - USA), P. SONG , K. JENKINS (IBM - USA), J-C. LO
(URI - USA) |
|
| 12:30-14:00 |
Lunch |
| 14:00-15:30 |
Session 3 |
| 14:00-15:30 |
Session 3.a: Design for Dependability |
| Moderator: R. VELAZCO, Tima - France, L.
IMPAGLIAZZO, Ansaldo Segnalamento Ferroviario SpA- Italy |
| F3.a.1 |
Application of Local Design-for-Reliability
Techniques for Reducing Wear-out Degradation of CMOS Combinational
Logic Circuits
X. XUAN, A. CHATTERJEE (Georgia Institute of Technology - USA),
A. SINGH (Auburn University - USA) |
| I3.a.2 |
Should We Make Our Design for Testability Schemes
Fault Secure?
C. METRA (Università di Bologna - Italy), TM MAK (Intel
Corp. - USA),
M. OMANA (University of Bologna - Italy) |
| F3.a.3 |
A New Self-checking Multiplier by Use of a
Code-disjoint Sum-bit Duplicated Adder
D. MARIENFELD, E. SOGOMONYAN, V. OCHERETNIJ, M. GOSSEL (University
of Potsdam - Germany) |
| |
|
| 14:00-15:30 |
Session 3.b: ATE Hardware and Software |
| Moderator: S. ERMOLLI, Agilent Technologies
- Italia, Y. BERTRAND, LIRMM - CNRS/Univ Montpellier 2 - France |
| F3.b.1 |
Software Development for an Open Architecture
Test System
B. PARNAS, A. PRAMANICK, M. ELSTON, T. ADACHI (Advantest
America R & D - USA) |
| I3.b.2 |
Highly Reconfigurable ATE for Rapidly Evolving
Test Requirements
B. WEST (NPTest - USA) |
| I3.b.3 |
Characterizing an SOC Digital
Channel as an Analog Reference Source
R. MCALEENAN (Agilent Technologies) |
|
| 15:30-16:30 |
Poster Session 2 |
| P2.1 |
Connecting Design&OBT
J. HUERTAS, G. HUERTAS, D. VÁZQUEZ, A. RUEDA (Instituto
de Microelectrónica de Sevilla - Spain) |
| P2.2 |
Adding Testability to an Asynchronous Interconnect for Globally-Asynchronous,
Locally-Synchronous Systems-on-Chip
A. EFTHYMIOU, J. BAINBRIDGE, D. EDWARDS (University of Manchester
- UK) |
| P2.3 |
A Built-In Mixed-signal Block Observer (BIMBO)
M. FELGUEIRAS , G. ALVES (ISEP - Portugal),
Jose FERREIRA (FEUP - Portugal) |
| P2.4 |
A Zero-Aliasing Test Response Analyzer Based on Berlekamp-Massey
Algorithm
C. SOUZA, R.C. FREIRE, F. ASSIS (UFCG - Brazil) |
| P2.5 |
Evolutionary Design of Synthetic RTL Benchmark Circuits
Z. KOTASEK, T. PECENKA, J. STRNADEL, L. SEKANINA (Brno University
of Technology - Czech Republich) |
| P2.6 |
Reusing Design Verification Tests in Manufacturing
M. WEISS, S. SETH (University of Nebraska-Lincoln - USA),
S. MEHTA (Indian Institute of Technology - India) |
|
| 16:30-18:00 |
Session 4 |
| 16:30-18:00 |
Session 4.a: Timing and Delay Testing |
| Moderator: A. ORAILOGLU, University of
California, San Diego - USA, W. DI PALMA, Magneti Marelli Powertrain
S.p.A. - Italy |
| F4.a.1 |
Delay Fault Testing and Silicon
Debug Using Scan Chains
R. DATTA (Computer Engineering Research Center - USA),
A. SEBASTINE, J. ABRAHAM (The University of Texas, Austin - USA) |
| F4.a.2 |
Manufacturing-Oriented Testing of Delay Faults
in the Logic Architecture of Symmetrical FPGAs
P. GIRARD, O. HERON, S. PRAVOSSOUDOVITCH, M. RENOVELL (LIRMM -
CNRS/Univ Montpellier 2 - France) |
| I4.a.3 |
Testing Multi-Bus System-on-Chip (SoC) Devices
R. YOUNGBLOOD, M. CHOWANETZ (Credence Systems Corporation - USA) |
| |
|
| 16:30-18:00 |
Session 4.b: MEMS Testing |
| Moderator: E. GRAMATOVA, Slovak Academy
of Sciences - Slovakia, Z. PENG, Linköping University - Sweden |
| F4.b.1 |
Electrically-Induced thermal Stimuli for MEMS
testing
N. DUMAS, F. AZAIS, L. LATORRE, P. NOUET (LIRMM - CNRS/Univ Montpellier
2 - France) |
| F4.b.2 |
MEMS Built–In-Self-Test Using MLS
A. DHAYNI, S. MIR, L. RUFER (TIMA - France) |
| F4.b.3 |
Test Planning and Test Resource Optimization
for Droplet-Based Microfluidic Systems
F. SU, S. OZEV, K. CHAKRABARTY (Duke University - USA) |
|
| 19:30-21:00 |
Dinner |
| 21:00-22:30 |
Evening Panels |
| 21:00-22:30 |
Panel 1.a: Patent or Perish? |
| |
Intellectual Property rights in the form of patents
play an increasing role, also in our test field. This topic is especially
of interest to companies, but also academics get every now and then
involved in patents, perhaps as inventor. Patents are important
w.r.t. standards, such as our test standards 1149.x, 1450.x, 1500,
etc. Large corporations trade their large patent rights portfolio
with "friends" under cross licenses, while starting infringement
cases against "enemies". For small start-ups, patents
might be the bread-and-butter, in order to prevent their customers
from simply copying their ideas for free. Also in cooperation contracts
between companies and universities, we see more and more clauses
on intellectual property rights. And finally: a long list of patents
on your resume brings every scientist fame as "inventor"!
Moderator: T. WILLIAMS (Synopsys, USA)
Introduction: N. WOLFF (European Patent Office,
The Netherlands)
Panelists:
R. BEKKERS (Eindhoven Univ. of Technology, The Netherlands)
E.J MARINISSEN (Philips Research, The Netherlands)
H. MANHAEVE, (QStar, Belgium)
J. RAJSKI, (Mentor Graphics, USA)
A. SINGH (Auburn University, USA)
Organizer: E.J. MARINISSEN (Philips Research,
The Netherlands)
|
| 21:00-22:30 |
Panel 1.b: Reducing Test Cost: How Much Multi-Site Can You
Handle? |
| |
Multi-site testing does not refer to testing at multiple geographical
locations, but to testing multiple copies of the same chip in parallel
on one test system. It is seen by many as THE way to reduce test costs.
Memory chips are typically tested in massive parallel numbers, and
increasingly also ASICs, SOCs, and microprocessors are tested this
way. What are the economic pros and cons of multi-site testing? Does
it really pay off that well? What are upper limits for fixtures and
handlers? Can DfT help in enabling multi-site testing, and if so,
how? What about analog multi-site testing? And, are there still issues
in which the research community might help the test engineering community
forward?
Moderator: B. BENNETTS (Bennetts Associates,
UK)
Panelists:
T. BOYDSTON (Teradyne, USA)
A. CROUCH (Inovys, USA)
R. ILLMANN (Cadence Design Foundry, UK)
H. LANG (Motorola, Germany)
P. MUHMENTHALER (Infineon Technologies, Germany)
B. WEST (NP Test, USA)
Organizers:
S. KUMAR (Philips Research, The Netherlands)
E.J. MARINISSEN (Philips Research, The Netherlands) |
|
| 08:30-10:00 |
Session 5 |
| 08:30-10:00 |
Session 5.a: Embedded Core Testing |
| Moderator: I. HARRIS, University of Massachusetts,
Amherst - USA, M. CASARSA, St Microelectronics - Italy |
| I5.a.1 |
A Novel Wrapper Cell Design for
Efficient Testing of Hierarchical Cores in System Chips
S. GOEL (Philips Research Laboratories - The Netherlands) |
| F5.a.2 |
User-Constrained Test Architecture Design for
Modular SOC Testing
L. KRUNDEL (ISIM - France), S. GOEL, E.J. MARINISSEN (Philips
Research - The Netherlands), M.L. FLOTTES ,
B. ROUZEYRE (LIRMM CNRS / Univ Montpellier 2 - France) |
| F5.a.3 |
Pipelined Test of SOC Cores Through Test Data
Transformations
A. ORAILOGLU, O. SINANOGLU (University of California at San Diego
- USA) |
| |
|
| 08:30-10:00 |
Session 5.b: Analog Building Block Testing |
| Moderator: L. BALADO SUAREZ, Polytechnic
University of Catalonia - Spain, B. KAMINSKA, Fluence Technology -
USA |
| I5.b.1 |
On the use of Genetic Algorithms for Fault
Diagnosis on Continuous-Time Analog Filters
C. SAVIOLI, C. SZENDRODI, J.V. CALVANO, (Brazilian Navy Electronics
Center - Brazil) |
| I5.b.2 |
Testing High Resolution SD ADC’s by using
the Noise Transfer Function
D. DE VENUTO (Politecnico di Bari-Italy - Italy), A. RICHARDSON
(Lancaster University - UK) |
| I5.b.3 |
A Wrapper for Testing Analog to Digital Converters
Cores in SoCs
J. MACHADO DA SILVA, J. BRAGA, J. MATOS (Univ. Porto - Portugal) |
|
| 10:00-11:00 |
Poster Session 3 |
| P3.1 |
Mixers under Vt Mismatch Defects: Detectability
by Constellation Plots
J. FIGUERAS, D. ARUMI DELGADO, R. RODRÍGUEZ MONTAÑÉS
(UPC - Spain) |
| P3.2 |
A Technique for Optimization of System-on-Chip Test Data
Transportation
A. LARSSON, E. LARSSON, P. ELES, Z. PENG (Linköpings Universitet
- Sweden) |
| P3.3 |
Limited-Resource Systems Testing with Microagent Societies
L. MICLEA, A. SZILARD, L. BUSONIU, M. ABRUDEAN (Technical University
of Cluj-Napoca - Romania), I. STOIAN (IPA Cluj-Napoca - Romania),
A. VANCEA (Technical University of Cluj-Napoca - Romania) |
| P3.4 |
A New Path Delay Test Scheme Based on Path Delay Inertia
C.L. LEE (National Chiao Tung University - Taiwan) |
| P3.5 |
The Influence of Cracks on Digital Superconductor Logic
A. JOSEPH, M. WEUSTHOF, H. KERKHOFF (MESA+ Research Institute
- The Netherlands) |
|
| 11:00-12:30 |
Session 6 |
| 11:00-12:30 |
Session 6.a: Test Resource Partitioning |
| Moderator: Y. ZORIAN, Virage Logic - USA,
B. AL-HASHIMI, University of Southampton - UK |
| F6.a.1 |
Relating Entropy Theory to Test
Data Compression
K. BALAKRISHNAN, N. TOUBA (University of Texas at Austin - USA) |
| F6.a.2 |
A Compression-Driven Test Access Mechanism
Design Approach
P. GONCIARI, B. AL-HASHIMI (University of Southampton - UK) |
| I6.a.3 |
Data Compression for Multiple Scan Chains Using
Dictionaries with Corrections
A. WUERTENBERGER, C. TAUTERMANN, S. HELLEBRAND (University of
Innsbruck - Austria) |
| |
|
| 11:00-12:30 |
Session 6.b: Fault Simulation and Verification |
| Moderator: M. ABADIR, Motorola, Inc. -
USA, D. PRADHAN, University of Bristol - UK |
| F6.b.1 |
Enhanced 3-valued Logic/Fault simulation for
full scan circuits using implicit logic values
S. KAJIHARA (Kyushu Inst. of Tech. - Japan), K. SALUJA (University
of Wisconsin-Madison - USA), S. REDDY (University of Iowa - USA) |
| I6.b.2 |
Fundamentals of a novel approach for mixed
analogue-digital verification
R. MARIANI, M. CHIAVACCI, G. BONFINI (YogiTech SpA - Italy) |
| F6.b.3 |
Signal Integrity Verification using High Speed
Monitors
V. AVENDAÑO, V. CHAMPAC (INAOE - Mexico)
J. FIGUERAS (UPC - Spain) |
|
| 12:30-14:00 |
Lunch |
| 14:00-15:00 |
Session 7: Embedded tutorial 1 |
| 14:00-15:00 |
Session 7.a |
| Moderator: J. FIGUERAS, Universitat
Politecnica de Catalunya - Spain, B. SCHNEIDER, Oticon - Denmark |
| |
Testing Quantum Circuits
J. HAYES (Univ Michigan - USA) |
| 14:00-15:00 |
Session 7.b |
| Moderator: L. CARRO, Universidade Federal
do Rio Grande do sul - Brazil, J. TYSZER, Poznan University of Technology
- Poland |
| |
Design Debug and Failure Analysis in the sub-quarter Micron Range
C. BURMER (Infineon Technologies - Germany) |
|
| 16:00-23:00 |
Social Event |
| 08:30-10:00 |
Session 8 |
| 08:30-10:00 |
Session 8.a: Analog BIST |
| Moderator: J.L. HUERTAS DIAZ, CSIC - Univ.
Sevilla - Spain, JP TEIXEIRA, INESC - Portugal |
| F8.a.1 |
Towards a BIST Technique for Noise
Figure Evaluation
M. NEGREIROS, L. CARRO, A. SUSIN (Univ. Federal do Rio Grande
do Sul - Brazil) |
| F8.a.2 |
A New BIST Scheme for 5GHz Low Noise Amplifiers
J.Y. RYU, B. KIM (Arizona State University - USA)
I. SYLLA (Texas Instruments - USA) |
| F8.a.3 |
All-pass SC biquad reconfiguration scheme for
oscillation based analog BIST
U. KAC, F. NOVAK (Jozef Stefan Institute - Slovenia) |
| |
|
| 08:30-10:00 |
Session 8.b: Memory Testing |
| Moderator: P. MUHMENTHALER, Infineon Technologies
AG - Germany, S. DEMIDENKO Monash University Malaysia - Malaysia |
| F8.b.1 |
Dynamic Read Destructive Fault in Embedded-SRAMs:
Analysis and March Test Solution
L. DILILLO, P. GIRARD, S. PRAVOSSOUDOVITCH, A. VIRAZEL (LIRMM
- CNRS / Univ Montpellier 2 - France),
S. BORRI, M. HAGE-HASSAN (Infineon Technologies France - France) |
| F8.b.2 |
Tests for Address Decoder Delay Faults in RAMs
due to Inter-gate Opens
A. VAN DE GOOR, S. HAMDIOUI, Z. AL-ARS (Delft University of Technology
- The Netherlands) |
| I8.b.3 |
A Fail-Silent Memory for Automotive Applications
T. KOTTKE (Robert Bosch GmbH - Germany), A. STEININGER (Tu Wien
- Austria) |
|
| 10:00-11:00 |
Poster Session 4 |
| P4.1 |
Built-in-Self-Test of a Charge-Pump
Based Phased Lock Loop : A Case Study oh High Speed Mixed Signal BIST
T. PATTNAYAK, S. BISWAS, S. MUKHOPADHYAY, A. PATRA, (Indian Institute
of Technology - India) |
| P4.2 |
Compression Methods for Path Delay Fault Test Pair Sets:
A Comparative Study
I. POLIAN, B. BECKER, A. CZUTRO (Albert-Ludwigs-Univ. of Freiburg
- Germany) |
| P4.3 |
Efficient Space/Time Compression of Test Data for Multiple
Scan Chain Designs
L. LI, K. CHAKRABARTY (Duke University - USA)
S. KAJIHARA (Kyushu Institute of Technology - Japan)
S. SWAMINATHAN (IBM Microelectronics - USA) |
| P4.4 |
Experiments with Arithmetic Built-In Self-Test Applied to a commercial Micro Controller Architecture
C. CORCELLI (Atmel Norway - Norway), E. AAS (Norwegian University
of Science and Technology (NTNU) - Norway), |
| P4.5 |
A Simple Logic Testing for Interconnect Opens
in CMOS Combinational Circuits
Y. MIURA (Tokyo Metropolitan University - Japan) |
|
| 11:00-12:30 |
Session 9 |
| 11:00-12:30 |
Session 9.a: Current-based Testing and Defect
Modeling |
| Moderator: B. STRAUBE, Fraunhofer Inst.
für Int. Schaltungen - Germany, F. NOVAK, Josef Stefan Institute
- Slovania |
| I9.a.1 |
Doing More with Less: A Recipe
for Rapid IDDQ development.
R. ACKERMAN (Sharp Microelectronics of the Americas - USA) |
| I9.a.2 |
New Defect Behavior at 130nm and Beyond
R. AITKEN (Artisan Components - USA) |
| I9.a.3 |
EEPROM Threshold Current Extraction: Silicon
Validation
H. AZIZA, Didier NÉE (ST-Microelectronics - France), J.M
PORTAL (L2MP-polytech - France) |
| |
|
| 11:00-12:30 |
Session 9.b: ATPG and High-Level Test |
| Moderator: M. ABRAMOVICI, DAFCA - USA,
A. CRON, Synopsis, Inc. - USA |
| F9.b.1 |
Functional Fault Coverage: the Chamber of Secrets
or an Accurate Estimation of Gate-Level Coverage?
F. FUMMI, C. MARCONCINI, G. PRAVADELLI (Università di Verona
- Italy) |
| I9.b.2 |
Defect Coverage Analysis of Partitioned Testing
S. CHAKRAVARTY, E. SAVAGE, E. TRAN (Intel Corporation - USA) |
| F9.b.3 |
Automatic Test Pattern Generation for Resistive
Bridging Faults
P. ENGELKE, I. POLIAN, B. BECKER, (Albert-Ludwigs-University
- Germany)
M. RENOVELL (LIRMM CNRS / Univ. Montpellier 2 - France) |
|
| 12:30-14:00 |
Lunch |
| 14:00-15:00 |
Session 10: Embedded Tutorial 2 |
| 14:00-15:00 |
Session 10.a |
| Moderator: J.L. CARBONERO, St Microelectronics
- France, R. SEGERS, Philips Semiconductors - The Netherlands |
| |
Test of RF Circuits and Systems
R. AITKEN (Artisan - USA) |
| 14:00-15:00 |
Session 10.b |
| Moderator: B. BECKER, University of Freiburg
- Germany, F. AZAIS, LIRMM - CNRS / Univ Montpellier 2 - France |
| |
Test standard - Historical Developments, Current
Status and Future Needs
A. CRON (Synopsis - USA) |
|
| 15:00-16:30 |
Session 11: Advances in DfT (Plenary) |
| Moderator: G. CARLSSON, Ericsson Radio
Systems AB - Sweden, A. BENSO, Politecnico di Torino - Italy |
| F11.1 |
A Design Methodology to Realize
Delay Testable Controllers Using State Transition Information
T. IWAGAKI, S. OHTAKE, H. FUJIWARA (Nara Institute of Science
and Technology - Japan) |
| F11.2 |
An Efficient Scan Tree Design
for Test Time Reduction
Y. BONHOMME, T. YONEDA, H. FUJIWARA (Nara Institute of Science
and Technology - Japan)
Patrick GIRARD (LIRMM - France) |
| I11.3 |
Efficient Pattern Mapping for Deterministic
Logic BIST
V. GHERMAN, H.J. WUNDERLICH, (Universität Stuttgart - Germany),
H. VRANKEN (Philips Research - The Netherlands),
F. HAPKE, M. WITTKE (Philips Semiconductors - The Netherlands) |
|
| 16:30-16:40 |
Closing Session (Plenary) |