ETS’04 offers four half-day TTEP 2004 tutorials.
The tutorial registration fees include participation to two among the four possible following tutorials.
Tutorial 1 (9:00-12:00) : 1149.1 Boundary
Scan Standards
Presenter :
Ben BENNETTS (Bennetts Associates – UK)
Intended Audience :
Design engineers (device and board); test engineers (device and board);
and their managers. Post-graduate research students.
Summary :
This tutorial, an introduction to the widely-accepted IEEE 1149.1-2001
Boundary Scan Standard, shows how boundary scan can be used to ease
the prototype debug and volume manufacturing test of loaded printed-circuit
board assemblies. The tutorial covers the basic chip-level architecture
and Boundary-Scan Description Language (BSDL) but the emphasis will
be on the use and benefits at board level, concentrating on pattern
generation for detection and diagnosis of faults within the boundary
scan domain. Handling faults outside the domain (non-boundary-scan device
and memory-array tests) is also considered, together with the specific
use of boundary-scan devices to program on-board flash memory.
Students receive a copy of the visuals plus associated text.
Keywords :
Board Test, Boundary Scan, 1149.1, JTAG, BSDL.
Tutorial 2 (9:00-12:00) : Image Sensors
and Optical Testing
Presenter :
Peter MAXWELL (Agilent - USA)
Intended Audience :
Design, test and manufacturing engineers and managers, students and
professors who would like to learn more about optical sensors, image
pipelines and how to test them.
Summary :
The goal is to expose attendees to the concepts of integrated optical
sensors, such as are used in lowcost cameras for cell phones. The first
part is an overview of image sensors, emphasizing CMOS technologies.
Changes to a standard CMOS process are described, together with design
requirements and methods and processing required to obtain a high quality
color image. Examples are given of camera modules in use in cell phones
today. Some color theory is then presented to give enough understanding
of the numerous aspects of image quality. This is followed by a discussion
of defect mechanisms which can occur throughout the manufacturing process,
from wafer fab, to module assembly, to focus and final test. Test methods
are developed to address these defects, in which optical blemish categories
are reviewed, together with a discussion of pixel correction algorithms
and what they can and cannot accomplish.
Keywords :
CMOS sensors, CCD, optical blemish, image quality, camera modules.
Tutorial 3 (14:00-17:00) : Practical Applications of boundary-Scan:
Single Board and Multiple-Board Systems
Presenter :
Ben BENNETTS (Bennetts Associates – UK)
Intended Audience :
Digital board/system and field-service designers and test engineers,
project managers, product support engineers. Post-graduate research
students.
Summary :
IEEE 1149.1 was originally intended to solve interconnect problems
on limited access boards. Boundary-scan now has a much wider application
to board and system test problems. Several companies supply support
devices that allow 1149.1 to be used as a backplane test bus. This
allows backplane interconnect test and multi-drop architectures, enabling
backplane-to-board-to-chip diagnostics in system integration and field
service scenarios. Additionally, the development of the IEEE 1532-2001
In-System Configuration Standard leverages 1149.1 structures to enable
programming of CPLDs and FPGAs in situ. The tutorial looks at all
these applications and others such as the new 1149.6-2003 “AC-EXTEST”
Standard. Students attending this tutorial will be assumed to be knowledgeable
about the 1149.1 Standard.
Keywords :
Boundary Scan, 1149.1, 1149.4, In-System Configuration, 1532, Board
Test, Backplane Test, 1149.6, AC-EXTEST.
Tutorial 4 (14:00-17:00) : Statistical Methods for VLSI Test, Quality and Reliability
Presenter :
Adit SINGH (Auburn University - USA)
Intended Audience :
VLSI Design and Test engineers, engineering managers, and researchers,
as well as reliability engineers and managers.
Summary :
VLSI circuits have been traditionally tested individually and independently
following manufacture. However, as the detection of delay defects,
and latent reliability flaws, becomes ever more challenging and expensive
in DSM circuits, innovative new statistical methods have been developed
in to improve test effectiveness and optimize test costs. Such methods
fall into two broad categories: those that exploit the statistics
of the variation of process and performance parameters on wafers,
and those that exploit the statistics of defect distribution on wafers.
This tutorial will present test methodologies that span both these
categories and illustrate their effectiveness with experimental results
from a number of recent studies on test and production circuits from
LSI Logic, IBM, Intel, TI and academia.
Keywords :
Delay, Defects, Faults, Test, Burn-in, Reliability, Quality.
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