Fringe Meeting

21 May 2006, 4-6pm in Chilworth Manor Hotel

For further information, please contact:

Dr. Ananta Kumar Majhi, Project Manager

Philips Research Lab. HTC-05, Room-3.049

5656 AE Eindhoven, The Netherlands

Tel: +31-40-27 43878

Fax: +31-40-27 44700

NanoTEST is a funded project by European MEDEA+ program. This project will create breakthroughs in manufacturing test, in the area of costs as well as achieved quality and time-to-market.

The project brings together four European microelectronics companies (AMIS in Belgium, Infineon in France and Austria, Philips in France and Netherlands, STM in France), four well-known institutes (CEA-LETI in France, INESC in Portugal, LIRMM in France, TIMA in France), three SMEs (Q-Star in Belgium, Tecmic in Portugal, Temento in France) and one tester company (Credence in France). The project duration is for four years (2005-2008) with more than 400 person-year involved in various activities.

This strong consortium will deliver new test methodologies as we enter the nano-technology era. Both future SoC technology nodes and future SiP packages are addressed. Accompanied by flows, tools and standards, the project results will be ready for exploitation on time to support emerging technologies. This will contribute significantly to the commercial success of the European microelectronics industry.

The project goals are:

· Low Cost: Reducing the cost of production testing by a factor of ten. The way to achieve this ambitious goal is to develop new methodologies that enhance tester throughput and reduce tester resources. For example, multi-site testing, low-cost test cells, advanced test interface boards, and test resource reduction by on-chip test provisions that go much further than current design-for-test practices. It is key now to determine the optimum balance between on-chip test provisions and off-chip test equipment.

· High Quality: Improving the quality of test, despite the fact that occurrence of new defect types in 65nm and 45nm will initially drive the defect levels up. This will be achieved by developing test methodologies for new defect types, as well as extending the use of tester data into the domain of fault diagnosis for fast production ramp-up, characterization and self-repair. Delay fault test strategies play an essential role in covering new defect types. The zero-defect programs driven by automotive, medical and aerospace industries demand quick diagnosis, new test development and test application in various stress conditions.

· Shorten Time-To-Market: Speeding up the complete design-for-test and test program generation flow by a factor of ten. This challenging goal can be achieved by deploying re-use at the optimum abstraction level. At the same time new methodologies will be developed for future designs, containing for example globally-asynchronous-locally-synchronous circuits, volatile and non-volatile memories, RF, mixed-signal blocks and sensors. Furthermore, tools will be developed to automate mixed-signal test specification and test program generation.