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Courtesy – Coventor inc. |
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In
Conjunction with European Test Symposium 2008 Workshop on Reliability & DfX Engineering
for System-in-Package Technologies http://www.cad.polito.it/~ets08/SiPeX |
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Grand
Hotel Majestic, Pallanza, Lago Maggiore, Italy Call for
Papers |
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Chair: A. Richardson, U. Co-Chair: P. Nouet, LIRMM, France Invited
Speakers (provisional) JM Yannou, NXP (Fr) H Kerkhoff, Uni Twente (NL) S Mir, TIMA (Fr) C Bailey, Uni Greenwich (UK) M Desmuliez, Heriot Watt Uni
(UK) I De Wolf, IMEC (Be) C Reeves, QinetiQ ( Sponsors
The FP6 Network of Excellence
in Design for Micro & Nano Manufacture
The
FP6 Integrated Project
“Integrated Micro & Nanotechnology Platforms and Services |
The SiPeX workshop aims to bring together reliability
and test engineers to discuss advanced design methodologies, integration
technology and assembly engineering for SiP solutions that embrace
heterogeneity, multiple energy domains and mixed technology platforms. Papers
are invited that address both current challenges and those expected in the
future in the following areas:
The
organising committee invites authors to submit both papers and poster
contributions in the above areas. Submissions should consist of either an
extended summary of at least 750 words or a full paper. The Workshop will take place
at the Grand Hotel Majestic,
Pallanza, Lago Maggiore, |
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Submission deadline : Monday 3rd March 2008 |
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Workshop
Chair Prof. Andrew Richardson Lancaster, LA1 4YR, UK Tel.: +44 1524 593018 Fax: +44 1524 592777 E-mail: a.richardson@lancaster.ac.uk |
Workshop Co-Chair Prof. Parscal Nouet University Montpellier II Montpellier, France Tel.: +33 467 418 527 E-mail: nouet@lirmm.fr |
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