The IEEE European Test Symposium (ETS) is Europe’s premier forum dedicated to presenting and discussing scientific results, emerging ideas, hot topics, and new trends, industrial case-studies and applications, in the area of electronic-based circuits and system testing, reliability, safety, security and validation. The 2021 edition of ETS will be a virtual one. The organizing team will strive to keep the spirit of ETS alive, by organizing an event with live sessions and many opportunities for networking and peer interaction. ETS’21 is organized jointly by KU Leuven and imec, which co-sponsor the event together with the IEEE Council on Electronic Design Automation (CEDA).
The program includes keynotes, scientific paper presentations, panels, tutorials, workshops and highlights/demos from industry.
Besides regular technical papers, ETS’21 provides the opportunity of submitting scientific contributions for Case-Study papers, presenting relevant industrial (or industrial collaboration) data that demonstrate a previously published concept, or that can help further research advancements. Papers submitted under this category should be of maximum 4 pages in the IEEE 2-column format.
You are invited to participate and submit your contributions to ETS’21. The areas of interest include (but are not limited to) the following topics:
| Analog, Mixed-Signal and RF Test | High-Speed I/0 Test |
| Approximate Circuit Testing | Low-Power Test |
| ATE Hardware and Software | Machine Learning and AI for Test |
| Automatic Test Generation | Memory Test and Repair |
| Automotive and Avionics Test | Microsystems / MEMS / Sensors Test |
| Board Test and Diagnosis | On-Line Test |
| Built-In Self-Test | Power- / Thermal-Aware Test |
| Current-Based Test | Processor Test (Multi-Core, GPU, CPU, Neuromorphic etc.) |
| Defect-Based Test | Security Issues in Test |
| Delay and Performance Test | Self-X (Awareness, Repair, Test, etc.) |
| Dependability and Functional Safety | Signal Integrity Test |
| Design for Test | SoC and NoC Test |
| DfX (Design for Manufacturing, Reliability, Yield, etc.) | Stacked or 3D ICs Test |
| Diagnosis and Silicon Debug | Standards in Test |
| Economics of Test | Test of Reconfigurable Systems (FPGA, CPLD, etc.) |
| Failure Analysis | Test, Reliability and Security of Emerging Technologies |
| Fault Modeling and Simulation | Test, Reliability and Security of Emerging Computing (Neuromorphic, In-Memory, Reversible and Quantum Circuits, etc.) |
| Fault Tolerance | Trojan Detection |
| Hardware Security | Verification and Validation |
| Hardware Trust | Yield Analysis and Enhancement |
Publications
ETS’21 will produce Formal Proceedings of scientific papers with ISBN number that will be included in the IEEE Xplore Digital Library. All accepted Case-Study papers will be included in the formal Proceedings, labeled as such.
Key Dates for Submissions
Submission deadline for title and abstract of case-study papers: December 10th, 2020
Submission deadline for full case-study papers: December 17th, 2020
Notification of acceptance: February 12th, 2021
Camera-ready manuscript and author registration: March 15th, 2021
Submissions
Submissions must be made using the submission website (link below).
Link to guidelines for this type of submission: Case-Sudy guidelines
A PDF version of this call for papers can be found here.">