Special Sessions

Special Session 1: Exploring and Comparing IEEE P1687.1 and IEEE 1687 Modeling and Implementation of NON-TAP Interfaces

In this special session, the contributors explore and differentiate IEEE 1687 from IEEE 1687.1. It starts with exploring and comparing the solutions based on privately extended IEEE 1687 and an equivalent solution based on IEEE P1687.1. Both use the IJTAG call-back feature, something rarely used. The former in an ad-hock way, the latter in a structured way as described in IEEE P1687.1, where the call-back is central. In a similar way, this methodology extends from IEEE P1687.1 into IEEE P2654. We close with a presentation of working examples of key features of an IEEE P1687.1 implementation, including such call-backs.
In summary, the industry is moving forward with answers to today’s problems based on today’s solutions, anticipating and implementing future IEEE P1687.1. This underlines the purpose, critical demand, and practicality of IEEE P1687.1 before it is even completely defined.

Organizers: Martin KEIM, Jeff REARICK

Monday, May 24th, 2021, 15:30 – 16:30 UTC+2
15:30 – 16:30 Hans-Martin VON STAUDT (Dialog Semiconductor – Germany)
Jeff REARICK (Advanced Micro Devices – USA)
Michele PORTOLAN (Univ Grenoble Alpes, CNRS, Grenoble INP1, TIMA – France)
Martin KEIM (Siemens Digital Industries Software – USA)

Special Session 2: Emerging Computing Devices: Challenges and Opportunities for Test and Reliability

Energy and power efficiency is undoubtedly one of the major driving forces of current computer industry, which is relevant for supercomputers on the one hand, as well as for small portable personal electronics and sensors on the other hand. Today’s computing devices are based on the CMOS technology that, thanks to the Moore’s Law, allowed performance increase coupled with fabrication cost reduction.
However, pushed by the forecasted end of Moore’s law, several emerging technologies (e.g., nanodevices, optical computing, quantum computing) are candidates to either replace or co-exist with the de facto standard CMOS technology. Moreover, technology is not the only root cause for the inefficiency of computing devices. In fact, the computing architecture itself is changing moving from the computation- to data- oriented paradigms in order to break the well-known “memory wall”.
Those new technologies and computing paradigms will not only change the way we used to design and program our computers, but also the way we used to test them to provide the required quality and reliability. Unfortunately this is not a straightforward process. For example, Artificial Intelligence applications shown relevant resilience properties to faults, meaning that the testing strongly depends on the application behavior rather than on the hardware structure. On the other hand, Approximate Computing even takes benefit from the wrong behavior of the hardware to reduce overheads. The consequence is that we may not have to test for all the possible faults but only for the “critical” ones. Finally, for some technologies such as quantum computing the concept of “behavior” is probabilistic therefore clearly impacting the concept of test.

Organizer: Alberto BOSIO

Monday, May 24th, 2021, 17:00 – 18:00 UTC+2
17:00 – 17:20 Quantum Accelerators: from quantum application to simulator execution
Koen Bertels (Qbee and University of Porto – Portugal)
Abstract: The talk will focus on the different layers that a quantum accelerator needs to have to be fully operational, both in development of quantum applications up to the execution on a quantum simulator to validate and verify the quality of the qubits. The challenges in quantum computing go from the highest algorithmic level up to the low-level electronics to control the analogue phenomena that are used in quantum computing.
Speaker bio: Koen Bertels current scientific research focuses on quantum computing and more specifically on the definition and implementation of a scalable quantum micro- and system architecture. He was a professor at Delft University of Technology working on the quantum topics. He is now at the University of Porto in Portugal and has created a company called QBee.eu. His work still involves specifying what the micro-architectural support is for the control of the quantum instructions and how the quantum accelerator is connected and integrated in a larger system design where classical logic is combined with quantum logic. The main approach focuses more on quantum accelerators and the full-stack definition that the QCA lab has defined and developed. In this context, we have defined a programming language, OpenQL, a template for the micro-architecture and the QBeeSim simulator platform to execute any quantum logic that can be defined. The google citation is 33.
17:20 – 17:40 Dependability for AI Hardware Architectures
Muhammad Shafique (New York University Abu Dhabi – UAE)
Abstract: Deep Learning (DL) has emerged as the state-of-the-art for many Artificial Intelligence (AI) applications. Now-a-days models trained using DL are being used/research for safety-critical applications where even a single failure can lead to catastrophic results. Therefore, it is vital to ensure the robustness of DNNs against a wide range of dependability threats that include hardware- induced threats such as soft errors, aging, and manufacturing defects. Traditional fault-mitigation techniques that are based on redundancy (e.g., Dual Modular Redundancy (DMR) and Triple Modular Redundancy (TMR)) are not effective for DNN-based applications due to their huge overheads arising from redundant hardware/execution of compute-intensive DNNs and synchronization issues. Other techniques such as Instruction Duplication (ID) and use of Error- Correcting Codes (ECC) also pose similar issues that lead to noticeable degradation in system’s performance and power-/energy-efficiency. To address this, alternate techniques need to be developed that exploit the intrinsic characteristics of DNNs to boost their fault -resilience at low cost. These techniques should be integrated in the current state-of-the-art systems without affecting their performance-/power-efficiency. Towards this, this talk will provides an overview of different techniques for enhancing the dependability of DNN-based systems against different vulnerabilities. It also covers how each technique can contribute to the overall resilience of a DNN- based system, and how can they be integrated to offer protection against a wide spectrum of hardware-induced dependability threats while incurring low design-time and run-time overheads. Towards the end, this talk highlights the key challenges on the road ahead towards developing dependable AI systems that offer desired level of protection against reliability threats.
Speaker bio: Muhammad Shafique received the Ph.D. degree in computer science from the Karlsruhe Institute of Technology (KIT), Germany, in 2011. Afterwards, he established and led a highly recognized research group at KIT for several years as well as conducted impactful collaborative R&D activities across the globe. In Oct.2016, he joined the Institute of Computer Engineering at the Faculty of Informatics, Technische Universität Wien (TU Wien), Vienna, Austria as a Full Professor of Computer Architecture and Robust, Energy-Efficient Technologies. Since Sep.2020, he is with the Division of Engineering, New York University Abu Dhabi (NYU-AD), United Arab Emirates, and is a Global Network faculty at the NYU Tandon School of Engineering, USA. His research interests are in design automation and system level design for brain-inspired computing, AI & machine learning hardware, wearable healthcare devices and systems, autonomous systems, energy-efficient systems, robust computing, hardware security, emerging technologies, FPGAs, MPSoCs, and embedded systems. His research has a special focus on cross-layer analysis, modeling, design, and optimization of computing and memory systems. The researched technologies and tools are deployed in application use cases from Internet-of-Things (IoT), smart Cyber-Physical Systems (CPS), and ICT for Development (ICT4D) domains. Dr. Shafique has given several Keynotes, Invited Talks, and Tutorials, as well as organized many special sessions at premier venues. He has served as the PC Chair, General Chair, Track Chair, and PC member for several prestigious IEEE/ACM conferences. Dr. Shafique holds one U.S. patent has (co-)authored 6 Books, 10+ Book Chapters, and over 300 papers in premier journals and conferences. He received the 2015 ACM/SIGDA Outstanding New Faculty Award, AI 2000 Chip Technology Most Influential Scholar Award in 2020, six gold medals, and several best paper awards and nominations at prestigious conferences.
17:40 – 18:00 Approximation-Based Fully Reliable TMR Alternative for Safety-Critical Applications
Marcello Traiola (Ecole Centrale de Lyon – France)
Abstract: In the last decade, Approximate Computing (AxC) has been studied as a possible alternative computing paradigm. AxC has been recently used to reduce the overhead cost of conventional fault tolerant schemes, such as the Triple Modular Redundancy (TMR). One of the most recent propositions is the concept of Quadruple Approximate Modular Redundancy (QAMR). QAMR reduces the overhead cost w.r.t. conventional TMR structures, while guaranteeing the same fault-tolerance capability. In this paper, we adopt a new approximation technique to realize the QAMR and we perform a Design Space Exploration (DSE) to find QAMR Pareto-optimal implementations. Moreover, we provide the design of a new majority voter adapted to the proposed architecture. Experiments show that for 97% of the examined circuits it was possible to find QAMR variants achieving a gain in terms of both area and delay (≈53%) or in terms of either of them (≈44%), compared to the TMR counterpart.
Speaker bio: Marcello Traiola received the Ph.D. degree in Computer Engineering from the University of Montpellier, France, in 2019 and the MSc Degree in Computer Engineering cum laude from the University of Naples Federico II, Italy, in 2016. He is currently a postdoctoral researcher at the Lyon Institute of Nanotechnology, Ecole Centrale de Lyon, in France. His main research topics are emerging computing paradigms with special interest in design, test, and reliability. He is an IEEE member.

Special Session 3: Recent Advances on Photonic Physical Unclonable Functions

Physical Unclonable Functions (PUFs) are a hardware-based response to the need of storage-free secret keys for secure authentication and for hardware integrity. Although their first demonstration in 2001 was of an optical nature, their success in the field of security is due to electronic implementations. One of the main reasons lies in the relative complexity of initial demonstrations where sophisticated experimental apparatus were required to generate the secret keys. Such implementations shared though many of the limitations common to other applications involving bulk optics such as the need for high alignment accuracy, low speeds, large footprint and high costs. In this special session we will see how the advances in integrated photonics and CMOS-compatible photonics, have led to photonic PUF solutions which are compact, low-cost and with a larger tolerance to alignment accuracy and fluctuations. Similarly, to electronic solutions, photonic PUFs are enabled by fabrication tolerances at a chip-level affecting majorly the performance of key photonic building blocks. These solutions may be readily integrated in hybrid or monolithic ways with electronic integrated circuits, thus efficiently interfacing with control electronics and post-processing electronic hardware to enable onchip cryptography-based solutions. Besides, photonic PUFs may exploit a larger number of degrees of freedom compared to more classical electronic solutions based on SRAMs, arbiters etc. thus potentially allow for more robust implementations against machine learning attacks. Different technology platforms will be discussed thus providing an overview of the current state-of-the-art in this active field of research.

Organizer: Fabio PAVANELLO

Wednesday, May 26th, 2021, 14:00 – 15:00 UTC+2
14:00 – 14:20 Can Optical PUFs Save Us? A Subjective Perspective
Ulrich Rührmair (University of Connecticut – USA)
Abstract: About two decades ago, so-called Physical Unclonable Functions (PUFs) were introduced as a new, physical security primitive. In particular Strong PUFs, which possess many challenge- response pairs and a highly complex challenge-response relation, have received considerable attention over the last years: They may not just serve as novel key storage method, but also as a powerful tool in more advanced protocols such as oblivious transfer or cryptographic key exchange. Unfortunately, however, almost all electrical or circuit-based Strong PUF candidates have been broken by machine learning attacks over time. Due to their higher entropy and more complex internal interactions, optical PUFs may “save” us in this situation, and may finally provide the secure resource that the community has been looking for. The talk provides a personal and subjective perspective on the general chances, but also the potential pitfalls that optical PUFs have to offer.
Speaker bio: Ulrich Rührmair is an Associate Research Professor at the University of Connecticut and also a member of LMU Munich. He has been working on PUFs and related topics in physical cryptography over more than 15 years, and has published around 80 articles in the area, among them various modelling attacks on electrical and optical Strong PUFs. He also the founder of the ASHES workshop at CCS.
14:20 – 14:40 Physical Keys in Silicon Photonics
Amy Foster (John Hopkins University – USA)
Abstract: Modern secure communications and authentication suffer from formidable threats arising from the potential for copying of secret keys stored in digital media. To address this vulnerability, a class of cryptographic devices known as physical unclonable functions (PUFs) are being developed. A user derives a digital key from a PUF’s physical behavior, which is sensitive to physical idiosyncrasies that are beyond fabrication tolerances and thus a PUF cannot be duplicated. Here we will present our nonlinear silicon photonic PUFs that are designed to strike a balance between the tremendous security offered by optical keys and the electronic compatibility of CMOS circuits. To “read” the devices light is coupled to and from the chaotic optical microcavity using robust single-mode waveguides formed in the same layer and telecommunications compatible hardware. We will discuss our PUF’s resistance to cloning during fabrication, repeatability and robustness, use as a source of large volumes of cryptographic key material, and resistance to modeling attacks using state-of-the-art methods such as deep neural networks.
Speaker bio: Amy C. Foster is currently an Associate Professor with the Electrical and Computer Engineering Department at the Johns Hopkins University, Baltimore, MD, USA. She has more than 40 journal publications and more than 70 conference proceedings in the area of silicon photonics. Her research has primarily focused on nanoscale control of silicon-based-integrated photonic waveguides for optimizing interactions such as nonlinear parametric processes. She is an Associate Editor of the OSA Journal Optics Express and a recipient of various awards including the DARPA Young Faculty Award, and the Johns Hopkins Catalyst and Discovery Awards.
14:40 – 15:00 Photonic Physical Unclonable Functions based on scattering random optical media: Optical Speckle response / key generation and its relation to the structured light input properties
Dimitris Syvridis (University of Athens – Greece)
Abstract: Optical scattering in random media is one of the most broadly accepted mechanisms for generation of challenge – response pairs in an optical physical unclonable function device (PUF). Each numerical input (challenge) of the PUF is converted to a specific spatial structure of light directed to the scattering medium. The strength of such a PUF depends on the number of different spatial encodings of the input light which result to uncorrelated optical speckles and in consequence different numerical responses. In this paper, a theoretical / numerical method for the calculation of the properties and the number of the different spatial structured optical inputs will be presented, together with the corresponding experimental evaluation. Some results on machine learning resistance of the above method will be also presented.
Speaker bio: Dr. Dimitris Syvridis is Photonics and Optical Communications Professor in the Dept. of Informatics and Telecommunications of the National and Kapodestrian University of Athens. He heads the Photonics Technologies and Communications Lab and he is active in the related scientific areas for more than 30 years. His current interests are mainly focused on Physical Layer Security for 5G and IoT systems including QKD applications.

Special Session 4: Security, Reliability and Test Aspects of the RISC-V Ecosystem

RISC-V has emerged as a viable solution on academia and industry. Pushed by the success of RISC-V, many other open source hardware projects have started and it is certainly to be expected that even more of them will start in the near future. However, to use open source hardware for safety critical applications, we need a deep understanding of the way in which well established mechanisms for testing reliability could be integrated and deployed on the RISC- V ecosystem, and we need a clear knowledge on how such an ecosystem can be leveraged to improve security. To this end, this special session addresses issues related with the use of RISC-V based architecture in the context of security, reliability and testing. The topics covered by the session are timely and of interest of the attendees of ETS. RISC-V and open hardware in general are gaining momentum, and their diffusion in secure and safety critical applications expose them to classical challenges related with security and reliability typical of these application domains. Recent results demonstrated the suitability of the platform for these applications, but several challenges are still far from being completely solved. It is thus of crucial importance that designers are fully aware of current limitations and possibilities associated with the use of the RISC-V platform in safety critical applications, to addressed and exploit them in a correct and effective way.

Organizer: Francesco REGAZZONI

Wednesday, May 26th, 2021, 18:30 – 19:30 UTC+2
18:30 – 18:45 How RISC-V can help in security research
Frank K. Gürkaynak (ETH Zurich – Switzerland)
Abstract: In relatively short time RISC-V has had a remarkable impact on both academia and industry, presenting many exciting opportunities especially when used in connection with open source hardware. However, the problems we face in the security field are not automatically solved by having access to an open ISA and open source implementation of this ISA. In this talk, I will present how our group leverages RISC-V and open source hardware for security research, and explain what works well and where we see issues at the moment.
Speaker bio: Frank K. Gürkaynak has obtained his Ph.D. Degree from ETH Zürich, and is working as a senior scientist in the Digital Circuits and Systems Group of Prof. Benini as well as leading the Microelectronics Design Center of ETH Zürich.
18:45 – 19:00 Thwarting Differential Power Analysis Attacks on RISCV processors
Michael Hutter, Elke De Mulder, Helena Handschuh (Rambus – USA)
Abstract: In this talk, after a short introduction on side-channel attacks such as Differential Power Analysis (DPA) and on how challenging it is to protect RISCV processors against physical attacks in general, we will provide an overview of the state of the art solutions including those proposed by industry such as our Rambus Secure RISCV core as well as those proposed by academia such as IAIK, ETH and WPI’s approaches. We will then discuss in more details how different solutions offer different levels of protection, most notably gate-level masking in hardware, software only based solutions, instruction set extensions that allow for DPA-hardened coprocessors, protocol level solutions etc. We also discuss hardware-software co-design. Furthermore, we address the question of how to efficiently test such protections, and which testing strategies might offer the best results. Finally, we leave the audience with some open problems such as memory protection, fault attack protection and RISCV processor input-output interface protections.
Speaker bio: Michael Hutter is a Senior Principal Engineer at Rambus, Inc. His current responsibilities include the technical lead of secure hardware developments, DPA resistant solutions, and advanced products. He holds a PhD degree in computer science from Graz University of Technology, Austria. From 2011 until 2014, he worked as a post-doctoral researcher and lecturer at TU Graz where he received a venia docendi (Habilitation) in applied information processing and communications in 2016. He has authored and co-authored 60+ conference and journal publications and had served on technical program committees of international cryptography and security conferences such as CHES, DATE, COSADE, CARDIS etc.
19:00 – 19:15 SW-only and HW/SW support for diverse redundancy for high-integrity applications
Jaume Abella (Barcelona Supercomputing Center – Spain)
Abstract: Common Cause Failures (CCFs), where a single fault can lead to a system failure, are a challenge for safety-related systems (e.g. avionics, automotive, space) where high integrity is mandatory. Dual Core LockStep (DCLS), where two cores provide redundancy with sufficient independence (i.e. diversity), is the default solution. However, such a solution halves the number of user-visible cores in multicores. Our research investigates SW-only and HW/SW solutions to enable diverse redundancy without needing strict DCLS. We will present our recent work and ongoing research to enable both types of solutions on both general-purpose multicores as well as GPUs.
Speaker bio: Jaume Abella is a Senior Researcher at the Barcelona Supercomputing Center (BSC) since 2009, and CEO of Maspatechnologies S.L. He holds a PhD degree by the Universitat Politecnica de Catalunya (2005). Jaume leads BSC activities in multiple projects related to the hardware and low-level software design for high-performance safety-related real-time embedded systems, including H2020 De-RISC, H2020 SELENE, ECSEL FRACTAL, H2020 SAFURE, and ARTEMIS VeTeSS, with particular focus on functional safety, reliability, timing V&V, and dependability in general. Jaume worked at Intel Corporation from 2005 to 2009. Jaume holds 13 patents, and has published 200 papers in international peer-reviewed conferences and journals.
19:15 – 19:30 Towards Bridging the Gap between System-level and Structural Test for the RISC-V Platform
Nourhan Elhamawy, Jens Anders, Steffen Becker, Matthias Sauer, Stefan Wagner, Ilia Polian (University of Stuttgart and Advantest – Germany)
Abstract: Microprocessors implementing the open RISC-V instruction set and systems-on-chip on their basis are increasingly being considered for safety-critical applications. A prerequisite for their acceptance in domains such as automotive is the feasibility of test procedures established in such domains. System-level test (SLT) is widely employed by both semiconductor manufacturers and system integrators to guarantee the required quality levels, based on procedures, data formats and protocols that have grown over time and are supported by multiple parties. This talk will discuss the specific challenges in making SLT part of an open ecosystem enabled by the RISC-V instruction set, where some of the information required for SLT may not exist. State-of-the-art RISC-V implementations are compatible with standard design flows, which enables a straightforward use of conventional structural test procedures and design-for-testability approaches. However, SLT comes with intricate challenges ranging from an appropriate definition of fault detection to assessing fault coverage of test content defined on the application and operating system level. One challenge is to understand what are the unique detections by different SLT programs and how to best combine different programs such as maximize coverage while keeping test duration realistic. To this end, we will present first results on coverages achieved by structural and system-level test approaches on a popular RISC-V processor implementation and its submodules.
Speaker bio: Ilia Polian IP is a Chaired Professor of Hardware-Oriented Computer Science and the Director of the Institute for Computer Engineering and Computer Architecture at the University of Stuttgart, Germany. He co-authored over 200 publications About test methods, hardware-oriented security and emerging architectures and received two best paper awards. He is the Speaker of the DFG Priority Program Nano Security.