Program at a glance
 

Approx.
Times
Tuesday
29.05
Wednesday
30.05
Thursday
31.05
Friday
01.06
08:00  
Registration
 
Registration    
08:30 Opening,
Keynote
Analog and
M-S Testing
IP* - Transportation of Test Data RTL Validation,
DFT and TPG
IP* -  Memory Testing
Tutorial 1
(09:00)
Tutorial 2
(09:00)
10:00 Break Poster 1 - Break Poster 3 - Break Poster 4 - Break
11:00 Tutorial 1 Tutorial 2 Defect-Oriented
Testing
IP* - System- Level DFT System-Level
Testing
IP* - Hierarchical
DFT
BIST and Test
Resource Partitioning
IP* - Mixed Signal
Testing
Report of Breakout Sessions
12:30 Lunch Lunch Lunch
Lunch on Boat
14:00 Tutorial 1 Tutorial 2 Delay Testing IP* - Core-based Testing and P1500 IP* - Logic BIST in Action
15:30 Break Poster 2 - Break Social Event Closing
16:30 Tutorial 1 Tutorial 2 IP* - Case Studies IP* - Full Scan  
18:00 Welcome Reception Dinner
20:30   Breakout Session
 
 
* IP - Industrial Practices