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Tutorial 1: Test Challenges in Nanometer Technologies
AUDIENCE: IC designers, test engineers, and their managers, also researchers, test methodology developers and test tool developers. SUMMARY: Testing has to address manufacturing defects, process marginalities and design marginalities. The techniques for addressing defects is still evolving while techniques for addressing process marginalities and design marginalities are at their infancy. This tutorial will give an overview of the state of the art in all three areas. The tutorial begins with an introduction to device and interconnect scaling and their implications and then moves on to strategies for dealing with emerging issues such as defect based testing and testing for process and design marginality related failures. KEYWORDS: Manufacturing defects, Interconnect Shorts-Opens, Process variation, Interconnect Coupling Impedance, Soft Error Technology Scaling, Defect Density | ||||
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