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Tutorial 2: Built-In Self-Test for Chips and System-on-a-Chip
AUDIENCE: Designers of complex systems-on-a-chip, IP core providers and integrators, test engineers, researchers, and managers interested in learning about state-of-the-art BIST technology, practices and automation tools. SUMMARY: This tutorial presents state-of-the-art BIST technology, practices and automation tools. It discusses compelling reasons as well as common barriers for its adoption. It covers guidelines for design of BIST-able cores, techniques for random pattern testability, as well as BIST architectures for random logic and memory arrays. Special emphasis is placed on issues related to at-speed testing, and BIST schemes for multi-frequency designs with on-chip generated clocks. The tutorial presents hierarchical BIST methodology for systems on silicon, based on BIST-ready IP cores and system BIST integration. Finally, the tutorial presents automation of BIST synthesis illustrated with applications and case studies. Attendees receive hard copies and a CD-ROM of the presented material. KEYWORDS: Logic Built-In Self Test, scan, BIST-ability rules and guidelines, random pattern testability, generators of pseudorandom patterns, compactors of responses, BIST schemes, at-speed multi-frequency testing, memory BIST, BIST automation | ||||
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