TECHNICAL PROGRAM

1. A Heuristic Method for CMOS Circuits Self-Checking Efficiency Estimation
   C. Quennesson, P. Debaud, E. Dupont-Nivet - CEA, France
   H. Mehrez - MASI, Univ. P et M Curie, France

2. BIST With Multiple On-chip Signature Comparisons
   M.F. Abdulla, C.P. Ravikumar, A. Kumar - Indian Institute of Technology, New Delhi, India

3. Testability Measure for Combinational Circuits when Random Testing
   V. Prepin, R. David - LAG / ENSIEG, France

4. Random Pattern Testability of AND/EXOR Expressions
   R. Drechsler, H. Hengster, B. Becker - Albert Ludwigs Univ, Frieburg, Germany
   H. Schafer - Johann Wolfgang Goethe University, Frankfurt / Main, Germany

5. Practical Problems of System Self-Test
   J. Sosnowski - Warsaw Univ. of Technology, Poland

6. A New Architecture for On-Line Selfchecking Circuits
   M. Riege - Philips Semiconductors, Hamburg, Germany, W. Anheier - Univ. of Bremen, Germany

7. A Method to Calculate a Deterministic Test Pattern Generator Based on Cellular Automata
   M.J. Lopez, M. Martinez, S. Bracho - Univ. of Cantabria, Spain

8. Self-Test of Integrated Circuit Wafers
   S. Chessa, P. Maestrini - Univ. di Pisa, Italy

Chair: Y. Zorian, Lucent Technology, USA

1. Scan-based BIST with Complete Fault Coverage and Low Hardware Overhead
   H.J. Wunderlich*, G. Kiefer - Univ. of Siegen, Germany

2. Condensed Circular Self-Test Path: A Low-Cost Circular BIST
   D. Badura, A. Hlawiczka* - Univ. of Gliwice, Poland

3. Enhancing Pseudo Exhaustive Test Set Quality by Code Bit Inversions
   J. Hlavicka* - Czech Technical University, Prague, Czech Republic
   O. Novak - Technical University, Liberec, Czech Republic

2:00pm-3:30pm: SESSION 3: Sensors for Thermal and Current Testing

Chair: Y. Burgess, Mentor Graphics, USA

1. Design of a BIC Monitor for Iddq Testing of CMOS VLSI Circuits
   V. Stopjakova*, B. Weber - Slovak Techn. Univ., Slovakia, H. Manhaeve - KHBO, Belgium

2. An Improved Switch for Keating-Meyer Iddq/Issq Testing
   X. Font*, J. Rius, J. Figueras - UPC Barcelona, Spain

3. An Approach to Dynamic Thermal Testing
   J. Altet*, A. Rubio - UPC Barcelona, Spain

1. A Sigma-Delta ADC for Analogue and Digital Test
   P.J. Mather, J. Raczkowycz - Univ. of Huddersfield, UK

2. A Practical Approach to Fault Localization in Crystal Oscillators
   M. Santo-Zarnik, S. Macek - Jozef Stefan Institute, Slovenia, F. Novak - Iskra RRI IEZE, Slovenia

3. A Balanced Approach to Dynamic Idd Monitoring for On-chip SelfTest of Current-mode Circuits
   M. Sidiropoulos, V. Musil - Techn. Univ. of Brno, Czech Republic, H. Manhaeve - KHBO, Belgium

4. Programmable Off-chip Iddq Monitor
   B. Straka, H. Manhaeve, J. Vanneuville - KHBO, Oostende, Belgium

5. A New Approach to Fault Diagnosis of Analogue Circuits Using Neural Networks Based Techniques
   V. Amarger, A. Bengharbi, K. Madani - Université Paris XII, France

6. Multi-Fault Diagnosis of Analog Circuits Using Multilayer Perceptron
   Y. Maidon, S. Lesage - IXL Laboratory, Bordeaux, France,
   B.W. Jervis, N. Dutton - Sheffield Hallam Univ., UK

7. Accounting for Device Mismatch in Analogue Circuit Testing
   E. Cantatore, F. Corsi, D. De Venuto - Politecnico di Bari, Italy

8. Estimation of Current Distribution in IDDQ Testing
   J.M. Diez, J.C. Lopez - Univ. Politecnica de Madrid, Spain

Chair: P. Teixeira, INESC, Portugal

1. High Fault Coverage Behavioral Test Generation
   Li.C. Wang*, M.R. Mercer - Univ. of Texas at Austin, USA, T.W. Williams - IBM, USA

2. Testing the Interconnect Strustures of Unconfigurated FPGA
   M. Renovell* - LIRMM, France, J. Figueras - UPC, Spain, Y. Zorian - AT&T Bell Labs, USA

3. Achieving High Reliability in Low Cost Parity Prediction Array Arithmetic Operators
   H. Bederr - Texas Instruments, France, M. Nicolaidis - TIMA/INPG, France, Y. Zorian - AT&T Bell Labs, USA

THURSDAY, JUNE 13

8:30am-10:00am: SESSION 5: Synthesis for Testability

Chair: B. Bennetts, Synopsys, UK

1. Testability Driven Synthesis of Non-Scan Data-Paths
   M.L. Flottes*, B. Rouzeyre - LIRMM, France

2. BELTA: a Tool for Handling Testability at the System Level
   F. Corno, P. Prinetto, M. Sonza Reorda - Politecnico di Torino, Italy

3. High-Level Test Specification for SFT Using Object-Oriented Modeling Techniques
   O.P. Dias, M. Calha, I.C. Teixeira, J.P. Teixeira - INESC, Portugal

1. Simplifying sequential gate-level test generation through exploitation of high-level information
   F. Ferrandi, F. Fummi - Politecnico di Milano, Italy
   E. Macii, M. Poncino, D. Sciuto - Politecnico di Torino, Italy

2. Local Transformations and Robust Dependent Path Delay Faults
   H. Hengster, B. Becker - Albert Ludwigs Univ., Freiburg, Germany
   S.M. Reddy - Univ. of Iowa, USA
   U. Sparmann - University of Saarland, Saarbruecken, Germany

3. Logic Optimization in Synchronous Circuits by using Topological ATPG Methods
   U. Glaser - GMD, Germany, K.T. Cheng - Univ. of Santa Barbara, USA

4. Test Automation using Z Specifications
   E. Mikk - Christian Albrechts Universitaet, Kiel, Germany

5. MOSA: a Multiple-Strategy Oriented Sequential ATPG
   A. Dargelas, C. Gauthron - COMPASS DA, France, Y. Bertrand - LIRMM, France

6. An Approach to Develop Testable Software
   S.Y. Wang, M. Ross, G. Staples, I. Court - Southampton Institute, UK

7. High Fault Coverage Behavioral Test Generation
   B. Benyo, A. Pataricza - Technical Univ. of Budapest, Hungary
   R. Vemuri - Univ. of Cincinnati, USA

8. Test Economics Criterion for Hardware/Software Partitioning
   Y. Le Traon, G. Al Hayek, C. Robach - LSR-IMAG, France

Chair: R. Ubar, Tallin Technical University, Estonia

1. Investigations on High-Level Control for Gate-Level ATPG
   W. Geisselhardt*, B. Emshoff, M. Kaibel - Univ. of Duisburg, Germany

2. High Level Test Pattern Generation for VHDL Circuits
   B. Sallay*, A. Petri, K. Tilly, A. Pataricza - Technical Univ. of Budapest, Hungary

3. How Efficient is the Software Mutation Test on the Hardware Implementation
   G. Al Hayek, C. Robach* - LSR-IMAG, France

3:30pm-6:00pm: SOCIAL EVENT

8:00pm-10:00pm: BANQUET

FRIDAY, JUNE 14

8:30am-10:00am: SESSION 7: Self Test of Components and Systems

Chair: S. Barbagallo, Italtel SpA, Italy

1. Deterministic BIST for Datapaths
   D. Gizopoulos, A. Paschalis - NCSR Athens, Greece, Y. Zorian - Lucent Bell Labs, USA

2. Self-Learning Signature Analysis for Non-Volatile Memory Testing
   P. Olivo*, M. Dalpasso - Universita di Ferrara, Italy

3. A Broad-Level Test Controller to Support a Hierarchical DFT Architecture
   J. Hakegard*,Z. Peng - Linköping Univ., Sweden, G. Carlsson - Microelectronics Ericsson Components, Sweden

1. Delay-Fault ATPG for High-Speed Electrically Erasable PLDs
   H. Kerkhoff, C. Klaasen, G. Van Brakel - MESA Research Institute, The Netherlands, M. Sachdev - Philips Research Labs., The Netherlands

2. The Minterm's Method. An Efficient Fault Model
   P. Debaud, E. Dupont-Nivet, C. Quennesson - CEA, France, H. Mehrez - MASI, Univ. Paris VI, France

3. Diagnostic Test Paterrn Generation for Delay Faults using TDgen
   G. Van Brakel, H.G. Kerkhoff - MESA Research Institute, The Netherlands

4. Design to Test (a.k.a. To Hell and back again)
   D. Bradly - LTX (Europe) Ltd., UK

5. A Diagnostic ATPG for Delay Faults Based on Genetic Algorithms
   P. Girard, C. Landrault, S. Pravossoudovitch, B. Rodriguez - LIRMM, France

6. On VHDL Defect Modeling and Simulation in CMOS Integrated Circuits
   F. Celeiro, L. Dias, J. Ferreira, M.B. Santos, J.P. Teixeira - INESC, Portugal

7. Interconnections Testing Problems with Consideration of Multiple Faults
   A. Kristof - Politechnika Slaska w Gliwicach, Poland

8. A New Floating Gate Fault Model for SPICE Fault Simulations
   A.J. Bishop, A. Ivanov - Univ. of British Columbia, Canada

Chair: H. Manhaeve, KHBO, Belgium

1. Quiescent Current Consumption in Defect-Free CMOS Registers
   A. Fere*, J. Figueras - UPC Barcelona, Spain

2. Quiescent Current Testing of Opens in Conducting Paths in FCMOS Circuits
   V. Champac* - Inst. National de Astrofisica, Puebla, Mexico, J. Figueras - UPC Barcelona, Spain

3. Iddq Test : Sensivity analysis of Scaling
   T.W. Williams*, R. Kapur - IBM, USA, M.R. Mercer - Texas A&M, USA,
   R.H. Dennard - IBM Yorktown, USA, W. Maly - CMU, Pittsburgh, USA

2:00pm-3:30pm: SESSION 9: Analog and Mixed Signal Testing

Chair: B. Courtois, TIMA, France

1. Analog DFT Technique Implementation: a Case Study
   M. Renovell, F. Azais*, Y. Bertrand - LIRMM, France

2. A broadband Test Method for A/D Converters
   M.T. Looijer*, A. Janssen, G. Seuren - Philips Research Laboratories, The Netherlands
   T. Zwemstra - Philips Semiconductor, The Netherlands

3. A hybrid technique for testing embedded S.C. filters in mixed signals ICs
   M. Robson*, G. Russell - The University of Newcastle Upon Tyne, UK