Moderator: P. Prinetto (Politecnico di Torino, Italy)

Keynote Address: "Creature from the Deep Sub-Micron Lagoon", Dr. Bernd Koenemann (LogicVision Inc., USA)

Title: FPGA and Memory Testing

Moderators: R. David (LAG, France) and B. Laquai (Hewlett-Packard, Germany)

Abstract: The first paper addresses the problem of testing the LUT/RAM modules of reconfigurable FPGAs. The second one combines error correcting codes and IDDQ testing in order to implement a reconfigurable fault-tolerant memory.

Papers:

"SRAM-BASED FPGAs: TESTING THE RAM MODE OF THE LUT/RAM MODULES", M. Renovell, J.M. Portal (LIRMM-UM2, France), J. Figueras (UPC, Spain), Y. Zorian (LogicVision Inc., USA)

"A FLEXIBLE MEMORY BLOCK RECOVERING STRATEGY USING MIXED ERROR CONTROL TECHNIQUES", O. Mocanu, J. Oliver (UAB, Spain)

SESSION I1 INDUSTRIAL PRESENTATIONS

Industrial Chair: B. Bennetts (Bennets Associates, U.K.)

Presentation 1: MENTOR (Mark Croft)

Presentation 2: LSI Logic (Maurizio Spadari)

SESSION I1 POSTERS

Poster Chair: M. Roca (UIB, Spain)

Posters:

"TEST TIME AND AREA TRADEOFFS BY ADJUSTING DESIGN SPACE SEARCH", K. Olcoz, J.F. Tirado (Univ. Complutense de Madrid, Spain), J.F. Santucci (Univ. of Corsica, France)

"EFFECTIVE SELF-TEST METHOD AND PATTERN GENERATION FOR FPGA-BASED RECONFIGURABLE SYSTEMS", T. Fukazawa, K. Kobayashi, K. Matsuhiro (NTT Optical Network Systems Labs., Japan)

"BOUNDARY-SCAN TECHNOLOGY, JUSTIFICATION, AND TEST IMPLEMENTATION FOR DESIGNERS", J. Phillips (Hewlett Packard Co., USA)

"ON IMPROVING BST FOR CONCURRENT FUNCTIONAL VERIFICATION", J.M. Vieira dos Santos(ISEP, Portugal), J.M. Martins Ferreira(FEUP, Portugal)

"DESIGN OF A CELLULAR AUTOMATION FOR EFFICIENT TEST PATTERN GENERATION", O. Novak (Technical Univ. Liberec, Czech Rep.), J. Hlavicka (Czech Technical Univ., Czech Rep.)

"BIST OF HARDWIRED AND GENERAL PURPOSE SERIAL/PARALLEL MULTIPLIERS", E.J. Aas (Norwegian Univ. of Science and Technology, Norway)

"EXPLORING DON'T CARES IN TEST PATTERNS TO REDUCE POWER DURING BIST", J.C. Costa, P.F. FLores, H.C. Neto, J.C. Monteiro, J.P. Marques da Silva(IST/INESC, Portugal)

Title: Scan-based BIST

Moderators: E. Aas (Norwegian Univ. of Science and Technology, Norway) and Z. Kohavi (Technion, Israel)

Abstract: This session addresses the scan-based BIST problem with three different objectives. First, to obtain complete fault coverage using deterministic patterns in a multiple scan environment. The second one is concerned with delay faults and the third tries to minimize power consumption during testing.

Papers:

"DETERMINISTIC BIST WITH MULTIPLE SCAN CHAINS", G. Kiefer, H.J. Wunderlich (University of Stuttgart, Germany)

"A NEW SCAN-BIST STRUCTURE TO TEST DELAY FAULTS IN SEQUENTIAL CIRCUITS", P. Girard, C. Landrault, V. Moreda, S. Pravossoudovitch, A. Virazel (LIRMM, France)

"LOW POWER SERIAL BUILT-IN SELF-TEST", A. Hertwig, H.J. Wunderlich (University of Stuttgart, Germany)

Title: Thermal and Analog testing

Moderators: B. Schneider (MicroLex, Denmark) and M. Glesner (Darmstadt University, Germany)

Abstract: The first paper gives an overview of basic concepts of thermal testing while the second focuses on a more specific application. The third paper deals with the integration of a CAD environment in order to decrease the cost of testing embedded analog blocks. The last paper describes a new off-chip diagnosis method to evaluate the jitter induced error in Analog to Digital converters.

Papers:

"VARIOUS ASPECTS OF THE DESIGN FOR THERMAL TESTABILITY (DfTT)", V. Székely, Cs. Márta (Technical Univ. of Budapest, Hungary), M. Rencz (MicReD Microelectronics, Hungary), B. Courtois (TIMA Lab, France)

"DIFFERENTIAL THERMAL TESTING: AN APPROACH TO ITS FEASIBILITY", J. Altet, A. Rubio (UPC, Spain), W. Claeys, S. Dilhaire, E. Schaub (Univ. Bordeaux, France), H. Tamamoto (Akita Univ., Japan)

"INTEGRATED DESIGN AND TEST OF MIXED-SIGNAL CIRCUITS", N. Engin, H. Kerkhoff, R. Tangelder, H. Speek (University of Twente, The Netherlands)

"OFF-CHIP DIAGNOSIS OF APERTURE JITTER IN FULL-FLASH ANALOG-TO-DIGITAL CONVERTERS", R. Rosing, H. Kerkhoff, R. Tangelder (Univ. of Twente, The Netherlands), M. Sachdev (Philips Research Labs., The Netherlands)

SESSION I2 INDUSTRIAL PRESENTATIONS

Industrial Chair: B. Bennetts (Bennets Associates, U.K.)

Presentation 1: "Tools for Testing Systems on Silicon", LogicVision (Y. Zorian)

Presentation 2: LogicVision (Michael Chapman)

SESSION I2 POSTERS

Poster Chair: J. Altet (UPC, Spain)

Posters:

"OPEN TESTABILITY OPTIMIZATION IN BICMOS GATES", V. Jiménez, R. Alcubilla (UPC, Spain)

"A MODELING STRATEGY FOR MIXED SIGNAL DEVICE TEST DEVELOPMENT", D. Apello (SGS Thomson Microelectronics, Italy), M. Ferretti, W. Narisoni (DIS, Univ. of Pavia, Italy)

"DESIGN OF TEST STRUCTURES FOR CMOS-COMPATIBLE SILICON PRESSURE SENSORS", S.A. Bota, E. Montané, J. Samitier (Univ. de Barcelona, Spain)

"THESIC: A TESTBED SUITABLE FOR THE QUALIFICATION OF INTEGRATED CIRCUITS DEVOTED TO OPERATE IN HARSH ENVIRONMENT", R. Velazco, Ph. Cheynet (TIMA Laboratory, France), A. Bofill (TIMA & UPC, Spain), R. Ecoffet (CNES, France)

"MIXED SIGNAL TEST OF COMMUNICATION ICs IN HIGH VOLUME-PRODUCTION ENVIRONMENT APPROACHES AND CHALLENGES", L.B. Sassoon (Level One Communications, USA)

"TIME-DOMAIN BASED TESTING OF A MIXED-SIGNAL TELEPHONE I.C.", D. De Venuto (Univ. of Lecce, Italy), F. Corsi (Polytechnic of Bari, Italy), M. Ohletz (Univ. of Hannover, Germany)

"STRUCTURAL TEST GENERATION FOR EMBEDDED ANALOG MACROS", V. Kaal, H. Kerkhoff, J. Hollema (Univ. of Twente, The Netherlands)

"TEST PATTERN GENERATION FOR THERMAL TESTING", H. Tamamoto, M. Saito (Akita University, Japan), A. Rubio, J. Altet (UPC, Spain)

Title: "BIST or BUST: Should the IC Fabs really hate BIST?"

Panel Coordinator: Keith Baker (Philips Research)

Panelists: M. Croft (Mentor Graphics), Volker_Schoeber (Siemens), K. Baker (Philips Research), C. Hawkins (Sandia Labs.)

Abstract: The DfT world has been pushing BIST for twenty or more years in IC design, and in the ASIC world at least is finally booking some success. However, in the both IC processing fabs and Assembly Test operations, BIST has a very negative image. What is the problem? Is BIST just a bad idea, that wastes area, impacts performance and provides too little information to control the process? Or are we at the final hurdle for BIST, get the diagnostic problem solved and the future of BIST is bright?

An informal reception to welcome ETW98 participants will be hosted by the Mayor in the Maricel Palace of Sitges.

Title: High Level Synthesis for Testability

Moderators: S. Hellebrand (Stuttgart University, Germany) and M-L. Flottes (LIRMM, France)

Abstract: The first paper presents an interesting application of incremental testability measures. The second one presents a method to improve testability during register allocation. The third paper targets an improved testability of the complete system by modifying the controller. The last paper identifies resources in the data path which can be used as test pattern generators and response evaluators.

Papers:

"INCREMENTAL TESTABILITY ANALYSIS FOR PARTIAL SCAN SELECTION AND DESIGN TRANSFORMATIONS", T. Yang, Z. Peng (Linköping University, Sweden)

"GUIDED HARDWARE SHARING PROCEDURE FOR IMPROVING TESTABILITY", M-L. Flottes, R. Pires, B. Rouzeyre (LIRMM, France)

"A NOVEL APPROACH TO HIGH-LEVEL TEST SYNTHESIS BASED ON CONTROLLER REDEFINITION", V. Fernández, P. Sánchez (Univ. Cantabria, Spain)

"OPTIBIST: A TOOL FOR BISTING DATAPATHS", D. Berthelot, M-L. Flottes, B. Rouzeyre (LIRMM, France)

SESSION I3 INDUSTRIAL PRESENTATIONS

Industrial Chair: B. Bennetts (Bennets Associates, U.K.)

Presentation 1: JTAG Technologies (Rik Doorneweert)

Presentation 2: OPMAXX (Bozena Kaminska)

SESSION I3 POSTERS

Poster Chair: A. Ferré (UPC, Spain)

Posters:

"IMPLICIT TESTABILITY TECHNIQUES FOR VHDL BASED ASIC DESIGN", M. Bombana, P. Cavalloro (Italtel, Italy), F. Ferrandi, F. Fummi, D. Sciuto (Politecnico di Milano, Italy)

"SWITCH-LEVEL FAULT SIMULATION AND TEST GENERATION FOR COMPETING BRIDGING FAULTS", K. Wiklund, T. Magnusson, P. Dahlgren (Chalmers Univ. of Technology, Sweden)

"AUTOMATIC FAULT DIAGNOSIS FOR CONTROL-FLOW BASED SYSTEMS", M. Khalil, Y. Le Traon, C. Robach (LCIS-ESISAR-INPG, France)

"MINIMAL TEST SETS FOR THE ELM ADDER", W. R. Moore (Oxford University, United Kingdom)

"COMBINING GAs AND SYMBOLIC METHODS FOR HIGH QUALITY TESTS OF SEQUENTIAL CIRCUITS", M. Keim, N. Drechsler, R. Drechsler, B. Becker (Albert-Ludwigs-University, Germany)

"TESTABILITY ANALYSIS OF BEHAVIORAL-LEVEL VHDL SPECIFICATIONS", E. Larsson, Z. Peng (Linköping University, Sweden)

"FEASILITY OF STRUCTURALLY SYNTHESIZED BDD MODELS FOR TEST GENERATION", J. Raik, R. Ubar (Tallinn Technical Univ., Estonia)

"A MODEL AND ALGORITHM FOR COMPUTING MINIMUN-SIZE TEST PATTERNS", P.F. Flores, H.C. Neto (IST/INESC, Portugal), K. Chakrabarty (Boston Univ., USA), J.P. Marques da Silva (IST/INESC, Portugal)

Title: Defect and Fault Modelling

Moderators: C. Hawkins (University of New-Mexico, USA) and J.L. Huertas (University of Sevilla, Spain)

Abstract: The first paper analyses the relationships between defects and fault models. The second paper studies defects arising in modern sub-micron technologies. The third one characterizes the electrical behaviour of floating gates in analog circuits.

Papers:

"ANALYSING RELATIONSHIP BETWEEN DEFECT AND FAULT MODEL", M. Renovell, F. Azaïs, Y. Bertrand (LIRMM, France)

"UNDERSTANDING OF THE FABRICATION PROCESS-KEY TO DESIGN AND TEST OF MIXED SIGNAL INTEGRATED CIRCUITS", M. d'Abreu, P. Isakanian, S. Hunjan (Level One Communications, USA)

"CHARACTERIZATION OF FLOATING GATE DEFECTS IN ANALOG CELLS", A.M. Brosa, J. Figueras (UPC, Spain)

The organization has planned a visit to the Picaso Museum and a walk through the Gothic Quarter on thursday afternoon. Before dinner participants will enjoy of a bus tour to some Gaudi buildings. The dinner will be held in a XIX century modernistic mansion. The visit and dinner are included in the registration fees. Additional tickets may be purchased at a cost of 10.000 pesetas.

Title: IDDQ Testing

Moderators: P. Maxwell (Hewlett-Packard, USA) and S. Bracho (University of Cantabria, Spain)

Abstract: This session addresses various aspects of IDDQ testing. The first paper deals with the evaluation of the off-state leakage current. The second ones describes a practical implementation of IDDQ for analog circuit testing. The third one proposes a new BIC sensor and the last uses IDDQ for localization of failures.

Papers:

"HIGH PERFORMANCE CMOS IC CHALLENGES IN IDDQ TESTING", C.F. Hawkins (Univ. of New Mexico, USA), A. Keshavarzi (Intel Corporation, USA), K. Roy (Purdue Univ., USA)

"ICCQ : A TEST METHOD FOR ANALOGUE VLSI BASED ON CURRENT MONITORING", J.P.M. van Lammeren (Philips Semiconductors, The Netherlands)

"A BUILT-IN CURRENT SENSOR USING MULTIPLE POWER SUPPLIES", Y. Miura, H. Yamazaki (Tokyo Metropolitan Univ., Japan)

"HIGH SPEED FAILURE LOCALIZATION WITH A NEW APPLICATION OF IDDQ TESTING", R. Desplats, B. Bertrand, P. Perdu, J. Benbrik, M. Dupire (CNES, France), F. Marc, Y. Danto (Univ. de Bordeaux, France)

SESSION I4 INDUSTRIAL PRESENTATIONS

Industrial Chair: B. Bennetts (Bennets Associates, U.K.)

Presentation 1: TEKTRONIX (Pere Fiter)

Presentation 2: HEWLETT PACKARD (Jean-Pierre Jauvion)

SESSION I4 POSTERS

Poster Chair: A.M. Brosa (UPC, Spain)

Posters:

"CLOCK SWITCHING: A NEW DESIGN FOR CURRENT TEST (DCT) METHOD FOR DYNAMIC LOGIC CIRCUITS", R. Rosing, H. Kerkhoff (Univ. of Twente, The Netherlands), A. Richardson (Lancaster Univ., U.K.), A. Acosta (Centro Nacional de Microelectrónica, Spain)

"RELIABILITY ANALYSIS FOR A POWER-SUPPLY CURRENT TEST", J. Argüelles, M.J. López (Univ. of Cantabria, Spain)

"TEST PATTERN GENERATION SYSTEM FOR IDDQ-VOLTAGE TEST EXPERIMENTS", E. Gramatová, A. Somorovská, J. Gaspar (Slovak Academy of Sciences, Slovakia), H. Manhaeve (KHBO, Belgium)

"DESIGN OF AN ON-CHIP DYNAMIC CURRENT SENSOR BASED ON CHARGE EVALUATION", R. Picos, M. Roca, E. Isern, J. Segura, E. García-Moreno (Univ. Illes Balears, Spain)

"HIGH SENSITIVITY CMOS BICS", Y. Maidon, Y. Deval, J-B. Begueret, J-P. Dom (Univ. Bordeaux, France)

"ESTIMATING DEFECT-FREE IDDQ FROM NOISY DATA", A. Ferré, J. Figueras (UPC, Spain)

"AN ON-CHIP DYNAMIC CURRENT MONITOR FOR IDDT TESTING", V. Stopjaková, V. Settey (Slovak Technical Univ., Slovakia), H. Manhaeve (KHBO, Belgium)

Title: Advances in High Level Testing

Moderators: M. Nicolaidis (TIMA, France) and R. Ubar (Tallin University, Estonia)

Abstract: The first paper presents a new methodology for assessing the quality of architecture solutions of hw/sw systems. The two last contributions examine the impact of software testing techniques on the improvement of high level test pattern generation.

Papers:

"METRICS FOR QUALITY ASSESSMENT OF TESTABLE HW/SW SYSTEMS ARCHITECTURES", O.P. Dias (EST, Portugal), I.C. Teixeira, J.P. Teixeira (IST/INESC, Portugal)

"HIERARCHICAL TEST PATTERN GENERATION: MOVING TOWARDS THE BEHAVIORAL LEVEL", S. Chiusano, F. Corno, P. Prinetto (Politecnico di Torino, Italy)

"AN ENHANCEMENT PROCESS FOR HIGH-LEVEL HARDWARE TESTING USING SOFTWARE METHODS", G. Al-Hayek, C. Robach (LCIS-ESISAR-INPG, France)

Industrial Chair: B. Bennetts (Bennets Associates, U.K.)

Presentation 1: "Boundary-scan, The Next Step: More Success", HEWLETT PACKARD (Jeff Phillips)

SESSION I5 POSTERS

Poster Chair: J. Argüelles (Univ. deCantabria, Spain)

Posters:

"DESIGN OF A NEW SIGNATURING ALGORITHM APPLIED TO A CONCURRENTLY ON-LINE ERROR DETECTING COPROCESSOR", O.D. Mocanu, J. Oliver (UAB, Spain), L. Teres (Centro Nacional de Microelectrónica, Spain)

"FIB CHIP REPAIR ASSISTED BY ELECTRICAL TESTING", R. Desplats, J. Benbrik, B. Benteo, P. Perdu (CNES-SOREP Lab., France), Y. Danto (IXL Lab., France)

"HIGH LEVEL SYNTHESIS APPROACHES FOR CONCURRENT ERROR DETECTION", C. Bolchini, W. Fornaciari, D. Sciuto (Politecnico di Milano, Italy), F. Salice (CEFRIEL, Italy)

"VHDL-BASED FAULT INJECTION FOR THE EARLY TESTING OF FAULT-TOLERANT SYSTEMS", J. Boué, J. Arlat, Y. Crouzet, P. Pétillon (LAAS-CNRS, France)

"A SOFTWARE-IMPLEMENTED FAULT INJECTION APPROACH FOR MICROPROCESSOR-BASED BOARDS", A. Benso, P. Prinetto, M. Rebaudengo, M. Sonza Reorda (Politecnico di Torino, Italy)

"SELF-CHECKING SYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN FOR UNIDIRECTIONAL ERROR", A. Y. Matrosova, S. Ostanin (Tomsk State University, Russia)

"STA: A SYSTEM TESTABILITY ASSISTANT", W. Maroufi, M. Marzouki (LIP6 Laboratory, France)

TECHNICAL SESSION 8

Title: Mixed topics in testing

Moderators: T. Williams (Synopsys, USA) and B. Becker (Freiburg University, Germany)

Abstract: The first paper combines classical scan with bus oriented testing. The second paper suggests new checkers for Borden codes under realistic fault model. The third paper addresses the problem of test pattern generation for delay faults in an industrial environment. The last paper deals with virtual testing.

Papers:

"INTEGRATION OF THE SCAN-TEST METHOD INTO AN ARCHITECTURE SPECIFIC CORE-TEST APPROACH", C. Feige, C. Wouters, (Philips Semiconductors, The Netherlands), J. ten Pierick, R.J.W.T. Tangelder, H.G. Kerkhoff (Univ. of Twente, The Netherlands)

"EFFICIENT HIGHLY TESTABLE BORDEN CODE CHECKERS", D. Nikolos, X. Kavousianos (Univ. of Patras, Greece)

"QUALITY DETERMINATION FOR GATE DELAY FAULT TESTS CONSIDERING THREE-STATE ELEMENTS", F. Pöhl, W. Anheier (University of Bremen, Germany)

"TESSI-DAVES: A COMMON ENVIRONMENT TO LINK DESIGN AND TEST OF MIXED SIGNAL ICs", E. Sax, K.-D. Müller-Glaser (Forschungszentrum Informatik Karlsruhe, Germany)