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| Session 9A: High Level Test | paper | slides | |
|---|---|---|---|
9A.1 |
RTL-based Functional Test
Generation For High Defect Coverage in Digital SoCs
M.B. Santos - F.M. Gonçalves - I.C. Teixeira - J.P. Teixeira IST/INESC, Portugal |
||
9A.2 |
Combining Symbolic and Genetic
Techniques for Efficient Sequential Circuit Test Generation
M. Boschini* - F. Fummi** - X. Yu' - E.M. Rudnick' * ST Microelectronics, Italy ** Università di Verona, Italy ' University of Illinois, USA |
|
|
9A.3 |
How to Avoid Random Walks
in Hierarchical Test Path Identification
Y. Makris - J. Collins - A. Orailoglu University of California San Diego, USA |
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