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| Session 9B: Memory Testing | paper | |
|---|---|---|
| 9B.1 | An effective distributed BIST
architecture for RAMs
A. Benso* - S. Chiusano* - S. Di Carlo* - G. Di Natale* - P. Prinetto* - M. Lobetti Bodoni** * Politecnico di Torino, Italy ** Siemens ICN, Italy |
|
| 9B.2 | Compressed Bit Fail Maps for
Memory Fail Pattern Classification
J. Vollrath - U. Lederer - T. Hladschik White Oak Semiconductor, USA |
|
| 9B.3 | A Memory Debug Methodology
Using BIST
L. Basto* - S. Menon** * Analog Devices, USA ** Intel, USA |
|
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