|
| Session 10A: BIST and Concurrent Testing | paper | |
|---|---|---|
| 10A.1 | A method for trading test
time, area and fault coverage in BIST synthesis
D. Berthelot - M.L. Flottes - B. Rouzeyre LIRMM, France |
|
| 10A.2 | Low Cost Concurrent Test
Implementation for Linear Digital Systems
I. Bayraktaroglu - A. Orailoglu University of California San Diego, USA |
|
| 10A.3 | On the Use of Multiple Fault
Detection Times in a Method for Built-In Test Pattern Generation for Synchronus
Sequential Circuits
I. Pomeranz - S.M. Reddy University of Iowa, USA |
|
|
