etw 2000: Session 1A

Session 1A: Delay Testing and Test Scheduling	paper	slides
1A.1	Bridging the Testing Speed Gap: Design for Delay Testability H. Speek * - H.G Kerkhoff * - M. Sachdev ' - M. Shashaani ' * MESA+ Research Institute, University of Twente, The Netherlands ' Department of Electrical and Computer Engineering, University of Waterloo, Canada	PDF
1A.2	Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences A. Virazel - R. David* ' - P. Girard * - C. Landrault * - S. Pravossoudovitch * * Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, Université Montpellier II / CNRS ' Laboratoire d'Automatique de Grenoble, INPG - CNRS - UJF	PDF
1A.3	List Scheduling and Tree Growing Technique in Power-Constrained Block-Test Scheduling Valentina Muresan - Xiaojun Wang School of Electronic Engineering, Dublin City University, Ireland Valentina Muresan - Mircea Vladutiu Faculty of Computer Science, "Politehnica" University of Timisoara, România	PDF	Part1.pdf Part2.pdf Part3.pdf

Session 1A: Delay Testing and Test Scheduling

paper

slides

1A.1

Bridging the Testing Speed Gap: Design for Delay Testability

H. Speek * - H.G Kerkhoff * - M. Sachdev ' - M. Shashaani '

* MESA+ Research Institute, University of Twente, The Netherlands

' Department of Electrical and Computer Engineering, University of Waterloo, Canada

PDF

1A.2

Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences

A. Virazel* - R. David ' - P. Girard * - C. Landrault * - S. Pravossoudovitch *