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| Poster Session P4: Test Pattern Generation | paper | slides | |
|---|---|---|---|
| P4.1 | Precise Test Generation for
Resistive Bridging Fault of CMOS Combinational Circuit
T. Maeda, K. Kinoshita Osaka University, Japan |
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| P4.2 | A New Data Structure for SAT-based
Static Learning with Impact on Test Generation
E. Gizdarsk* - H. Fujiwara** * University of Rousse, Bulgaria ** Nara Institute of Science and Technology, Japan |
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| P4.3 | A Constraint Programming Approach
to Model ATPG Related Problems
F. Azevedo - P. Barahona UNL, Portugal |
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| P4.4 | ATPG for Iddq and/or Voltage
Testing of Combinational Circuits Using an Arbitrary Fault Library for Basic
Gates
E. Gramatovà - T. Cibàkovà - J. Gaspar - P. Miklos Slovak Academy of Sciences, Slovakia |
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| P4.5 | Fault Oriented Test Pattern
Generation for Sequential Circuits Using Genetic Algorithms
E. Ivask - J. Raik - R. Ubar Tallinn Technical University, Estonia |
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| P4.6 | A Non-Scan Testable Design
of Sequential Circuits
H. Tamamoto - K. Usami - K. Seki - H. Yokoyama Akita University, Japan |
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