ETW'03
Technical Program
SUNDAY
May 25, 2003
8:00 - 9:00 REGISTRATION TUTORIALS AND WORKSHOP
9:00
- 17:00 TUTORIALS
T.1 |
Testing
(Embedded) Memories: New Fault Models, Tests, DfT, BIST, BISR, and
Industrial Results
A.J. van de Goor (Delft Univ. of Technology, NL) |
T.2 |
Defect-Oriented
Testing
P. Maxwell (Agilent Technologies, USA), R. Aitken (Artisan Components,
USA) |
16:00 - 22:00 WORKSHOP REGISTRATION
20:00 - 22:00 WELCOME BUFFET with ETTTC MEETING
MONDAY
May 26, 2003
7:30 - 8:30 WORKSHOP REGISTRATION
8:30
- 10:00 OPENING SESSION (Plenary)
Moderator:
G. Carlsson (Ericsson, S)
Welcome
E.J. Marinissen (Philips Research, NL), General Chair
Program
Introduction
S. Hellebrand (University of Innsbruck, A), Program Chair
Keynote
Address
DfT in Deep Submicron Process Monitoring
W.P. Maly (Carnegie Mellon University, USA)
Abstract:
Deep Submicron (DSM) technologies will soon enable fabrication of a billion
transistors IC. To test such IC the application of DfT is the only way to go.
But, DfT decreases failure observability. Poor failure observability, in turn,
causes problems in process development and yield learning - two basic
ingredients of a healthy DSM operation. In this presentation trade-offs between
IC testability and failure observability will be discussed. Vision of DfT based
process monitoring allowing for on-line failure characterization will be
proposed as well.
10:00 - 11:00 POSTER SESSION 1
Moderator:
F.
Azais (LIRMM, F)
P1.1 |
Prove and
Improve - Experiences with Formal Property Verification
Ø.
Gjermundnes, E.J. Aas (Norwegian University of Science and Technology, N) |
P1.2 |
Perfect
Conservation of Diagnostic Information in Aggressive Reduction of SOC Test
Bandwidth and Use
B. Arslan, A. Orailoglu (University of California, USA) |
P1.3 |
Fault
Tolerant Design of Random Logic Based on a Parity Check Code
S. Almukhaizim, Y. Makris (Yale University, USA) |
P1.4 |
A
Parametric-Stability Fault Model for Embedded SRAMs
A. Pavlov, M. Sachdev (University of Waterloo, CAN), J. Pineda de Gyvez
(Philips Research, NL) |
P1.5 |
Testing
of High Resolution ADCs with Deterministic and Stochastic Signals
J. Vedral, J. Holub (Czech Technical University, CZ) |
P1.6 |
Detection
of Resistive Shorts in Deep Sub-Micron Technologies
B. Kruseman (Philips Research, NL) |
P1.7 |
Test
Concept for Digital I/O with Reduced Number of High Performance Tester
Channels
H.-D. Oberle, S. Sattler (Infineon Technologies, D)
|
P1.8 |
PCI
Express™: ATE Requirements and DfT Features for Functional Test
Optimization
H. Werkmann (Agilent Technologies, D) |
P1.9 |
Optimization
Techniques for Parallel Interface of Test Wrapper for Embedded Cores
M. Balaz, E. Gramatova (Slovak Academy of Sciences, SLO) |
11:00
- 12:30 SESSION 1A DFT & BIST
Moderators:
J. Tyszer (Poznan
University of Technology, PL),
J.P. Hayes (University of Michigan, Ann Arbor, USA)
1A.1 |
TPI
for Improving PR Fault Coverage of Boolean and Three-State Circuits
M.J. Geuzebroek, A.J. van de Goor (Delft University of Technology, NL)
|
1A.2 |
On
the Selection of Efficient Arithmetic Additive Test Pattern Generators
S. Manich, L. Garcia, L. Balado, E. Lupon, J. Rius, R. Rodriguez, J.
Figueras (Universitat Politecnica de Catalunya, E) |
1A.3 |
Parity-Based
Output Compaction for Core-Based SOCs
O. Sinanoglu, A. Orailoglu (University of California, USA) |
11:00
- 12:30 SESSION 1B Memory Test
Moderators:
H.-J.
Wunderlich (University of Stuttgart, D), D. Adams (Pleiades Design and Test, USA)
1B.1*
|
Defect-Oriented
Dynamic Fault Models for Embedded-SRAMs
S. Borri (Infineon Technologies, F), M. Hage-Hassan (Infineon Technologies
& ISIM, F),
P.Girard, S. Pravossoudovitch, A. Virazel (LIRMM, F)
|
1B.2 |
Importance of
Dynamic Faults for New SRAM Technologies
S. Hamdioui (Delft University of Technology, NL & Intel, USA), R.
Wadsworth (ST Microelectronics, F), J.D. Reyes (Intel, USA), A.J. van de
Goor (Delft University of Technology, NL) |
1B.3*
|
Yield Analysis
for Repairable Embedded Memories
A. Sehgal (Duke University, USA), A. Dubey (Indian Institute of
Technology, New Delhi, India), E.J. Marinissen (Philips Research, NL), C.
Wouters (Philips Semiconductors, NL), H. Vranken (Philips Research, NL),
K. Chakrabarty (Duke University, USA) |
12:30
- 14:00 Luncheon
14:00
- 15:30 Session 2A Analog Test
Moderators:
M.
Lubaszewski (Universidade Federal do Rio Grande do Sul, BR), F.
Novak (Jozef Stefan Institute, SLO)
2A.1 |
Scan
Test Strategy for Asynchronous-Synchronous Interfaces
O. Petre, H.G. Kerkhoff (University of Twente, NL)
|
2A.2 |
A
New Methodology for ADC Test Flow Optimization
M. Comte, S. Bernard, F. Azaïs, Y. Bertrand, M. Renovell (LIRMM, F) |
2A.3 |
EEPROM
Memory: Threshold Voltage Built In Self Diagnosis
J.M. Portal (L2MP-Polytech, F), H. Aziza (L2MP-Polytech & ST
Microelectronics, F), D. Née (ST Microelectronics, F) |
14:00
- 15:30 Session 2B Embedded Tutorials
Moderators:
K.
Kinoshita (Osaka Gakuin University, J), W. Anheier (University of Bremen, D)
2B.1 |
Software
Implemented Fault Tolerance
A. Benso, P. Prinetto (Politecnico di Torino, I)
|
2B.2
|
Test
Considerations for Scaled CMOS Circuits
J.A. Abraham (University of Texas at Austin, USA), K. Roy (Purdue
University, USA) |
15:30
- 16:30 Poster Session 2
Moderators:
S.
Pravossoudovitch (LIRMM, F), Z. Kotasek (Brno University of Technology, CZ)
P2.1 |
Analysis
of Dynamic Behavior of Bridging Faults in CMOS Sequential Circuits
Y. Miura, S. Seno (Tokyo Metropolitan University, J)
|
P2.2 |
A
DC-Test Generation Approach to Nonlinear Analogue Networks by means of
Nullators and Norators
B. Straube, W. Vermeiren (Fraunhofer Institut für Integrierte
Schaltungen, D) |
P2.3 |
A
Programmable BIST Approach for the Diagnosis of Embedded Memory Cores
D. Appello (ST Microelectronics, I), P. Bernardi (Politecnico di
Torino, I), A. Fudoli (ST Microelectronics, I), M. Rebaudengo (Politecnico
di Torino, I), M. Sonza Reorda (Politecnico di Torino, I), V. Tancorre (ST
Microelectronics, I), M. Violante (Politecnico di Torino, I) |
P2.4 |
Test
Pattern Decompression Technique for Circuits with Scan
O. Novak, J. Zahradka (Technical University of Liberec, CZ) |
P2.5 |
Y-CAN
Platform: A Re-usable Platform for Design, Verification and Validation of
CAN-Based Systems On a Chip
A. Di Blasi, F. Colucci, R. Mariani (YogiTech, I) |
P2.6 |
Doubling
Memory Tester Capability by Efficient Expansion of Hardware and Software
H. Schulz (Infineon Technologies, D), M.G. Wahl (University of
Siegen, D) |
P2.7 |
BDD
Based Synthesis of Symmetric Functions with Full Path-Delay Fault
Testability
J. Shi, G. Fey, R. Drechsler (University of Bremen, D) |
P2.8 |
Built-In
Self-Test of Linear Time Invariant Systems
L. Rufer, E. Simeu, S. Mir (TIMA, F) |
P2.9 |
Realistic
Fault Behavior-Oriented Testing of Flash Memory
A. Keshk (Menofyia University, EGY) |
P2.10 |
Web
Based / Wireless BIST Management for Distributed Systems
L. Miclea, E. Szilárd, G. Toderean, I. Stoian (Technical University of
Cluj-Napoca, RO) |
16:30
- 18:00 Session 3A SoC Testing
Moderators:
B.M.
Al-Hashimi (University of Southampton, UK), E. Volkerink (Agilent
Technologies, USA)
3A.1 |
An
Efficient Approach to SoC Wrapper Design, TAM Configuration and Test
Scheduling
J. Pouget, E. Larsson, Z. Peng (Linköping University, S), M.-L.
Flottes, B. Rouzeyre (LIRMM, F)
|
3A.2 |
Power-aware
NoC Reuse on the Testing of Core-based Systems
E. Cota, L. Carro, F. Wagner, M. Lubaszewski (Universidade Federal do
Rio Grande do Sul, BR) |
3A.3 |
Control-Aware
Test Architecture Design for Modular SOC Testing
S.K. Goel, E.J. Marinissen (Philips Research, NL) |
16:30
- 18:00 Session 3B Issues in Test Application
Moderators:
R.
Segers (Philips Semiconductors, NL), K. Luther (Infineon Technologies, D)
3B.1* |
Analysis
and Modeling of Power Supply Related Failures
S. Sur Kolay (Indian
Statistical Institute, India), C. Tirumurti, S. Kundu, Y.-S.
Chang, S. Zachariah (Intel, USA)
|
3B.2* |
A
Practical Evaluation of IDDQ Test Strategies for Deep Submicron Production
Test Application: Experiences and Targets from the Field
A. Fudoli, A. Ascagni, D. Appello (ST Microelectronics, I), H. Manhaeve
(Q-Star Test, B) |
3B.3* |
Automating
the Device Interface Board Modeling for Virtual Test
M. Rona, G. Krampl (Infineon Technologies, A), F. Raczkowski (FH
Johanneum Kapfenberg, A) |
18:30
- 20:30 Dinner
20:30
- 22:00 Breakout Sessions
Organizer:
H.G. Kerkhoff (University of Twente, NL)
B.1 |
SoC
Test in Education: Dream or Nightmare?
Moderators: B.M. Al-Hashimi (University of Southampton, UK), A.
Richardson (University of Lancaster, UK)
|
B.2 |
Infrastructure
IP: Help or Burden?
Moderators: Y. Zorian (Virage Logic, USA), J. Rajski (Mentor Graphics, USA) |
B.3 |
SoC
Research is Sexy; Board Test is Not!! Why?
Moderators: G. Carlsson (Ericsson, S), B. Bennetts (Bennetts Assoc.,
UK) |
B.4 |
Can
Design Verification be (Re)Used for Manufacturing Testing?
Moderators: F. Fummi (University of Verona, I), P. Sanchez (University
of Cantabria, E) |
TUESDAY,
May 27, 2003
8:30 - 10:00 Session 4A Defect-Oriented Test
Moderators:
M.
Sachdev (University
of Waterloo, CAN), P. Maxwell (Agilent Technologies,
USA)
4A.1 |
Signal
Integrity Loss in Bus Line due to Open Shielding Defects
V. Avendaño, V. Champac (National Institute for Astrophysics, Optics
and Electronics, MEX), J. Figueras (Universitat Politecnica de Catalunya,
E)
|
4A.2 |
Process-Variability
Aware Delay Fault Testing of DVT and Weak-Open Defects
D. Arumí-Delgado, R. Rodríguez-Montañés (Universitat Politecnica de
Catalunya, E), J. Pineda de Gyvez, G. Gronthoud (Philips Research, NL) |
4A.3 |
Modeling
Feedback Bridging Faults with Non-Zero Resistance
I. Polian, P. Engelke (University of Freiburg, D), M. Renovell (LIRMM,
F), B. Becker (University of Freiburg, D) |
8:30
- 10:00 Session 4B ATPG
Moderators:
H.
Fujiwara (Nara Institute of Science
and Technology, J), A. Chichkov (AMIS, USA)
4B.1 |
Optimal
Interconnect ATPG under a Ground-Bounce Constraint
H.D.L. Hollmann, E.J. Marinissen, B. Vermeulen (Philips Research, NL)
|
4B.2* |
Automating
Test Program Generation in STIL - Expectations and Experiences using IEEE
1450
H. Lang, B. Pande, H. Ahrens (Motorola, D) |
4B.3* |
Pattern
Generation Using Neural Network & Genetic Algorithm For Estimation of
Switching Noise on Power Supply Lines in CMOS Circuits
E. Liau (Infineon Technologies, D), D. Schmitt-Landsiedel (TU Munich,
D) |
10:00
- 11:00 Poster Session 3
Moderators:
O.
Novak (Technical University in
Liberec, CZ), M.
Lobetti-Bodoni (Siemens, I)
P3.1 |
Software-Based
Testing of Sequential VHDL Descriptions
M. Scholivé, V. Beroulle, C. Robach (LCIS-ESISAR, F), M.-L. Flottes,
B. Rouzeyre (LIRMM,
F)
|
P3.2 |
A
Test Chip for Contact and Via Failure Analysis for 90-nm Copper
Interconnect CMOS Technology
A. Cabrini (University of Pavia, I), P. Cappelletti, D. Iezzi, M.
Pasotti, A. Maurelli (ST Microelectronics, I), G. Torelli (University of
Pavia, I) |
P3.3 |
Online
Testing of Interconnect Faults in SRAM Based FPGA Systems
L. Kalyan Kumar, A.J. Mupid, A.S. Ramani, V. Kamakoti (Indian Institute
of Technology, Madras, India) |
P3.4 |
On
the Compaction of Independent Test Sequences for Sequential Circuits
P. Drineas (Rensselaer Polytechnic Institute, USA), Y. Makris (Yale
University, USA) |
P3.5 |
Test
Synthesis for Datapaths Using Datapath-Controller Functions
M. Inoue, K. Suzuki, H. Okamoto, H. Fujiwara (Nara Institute of Science
and Technology, J) |
P3.6 |
Detecting
Delay Defects in Slack Intervals Using Multiple Higher Clock Frequencies
and Results from Neighboring Die
A.D. Singh, H. Yan (Auburn University, USA) |
P3.7 |
An
Algorithm for ADC's Harmonic Estimation Suitable for Preliminary BIST
Operations
H. Sousa Mendonça, J. Machado da Silva, J. Silva Matos (INESC, P) |
P3.8 |
At-speed
Testing for Resistive-Open Defect in Address Decoder of Semiconductor
Memories
M. Azimane, A.K. Majhi, G. Gronthoud (Philips Research, NL), S.
Eichenberger (Philips Semiconductors, NL)
|
P3.9 |
Object-Oriented
Test Pattern Generator with Hybrid Algorithms
C.Y. Ooi (Universiti Teknologi Malaysia, MAL) |
P3.10 |
Column-Matching
BIST Exploiting Test Don't-Cares
P. Fiser, J. Hlavicka†,
H. Kubatova (Czech Technical University, CZ) |
11:00
- 12:30 Session 5A Miscellaneous
Moderators:
T.
Margaria (University of Dortmund, D),
A.
Steininger (TU
Vienna, A)
5A.1* |
Infrastructure
IP for Back-End Yield Improvement
L. Forli (L2MP-Polytech, F), J.M. Portal (L2MP-Polytech & ST
Microelectronics, F), D. Née, B. Borot (ST Microelectronics, F)
|
5A.2 |
Code
Generation for Functional Validation of Pipelined Microprocessors
F. Corno, G. Squillero, M. Sonza Reorda (Politecnico di Torino, I) |
5A.3 |
Data
Criticality Estimation in Software Applications
A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto, L. Tagliaferri
(Politecnico di Torino, I) |
11:00
- 12:30 Session 5B Embedded Tutorials
Moderators:
R. Ubar
(Tallinn Technical University, EE), H.-J. Wunderlich (University
of Stuttgart, D)
5B.1 |
Statistical
Methods for VLSI Test and Burn-In Optimization
A.D. Singh (Auburn University, USA)
|
5B.2 |
Infrastructure
IP for SOC
Y. Zorian (Virage Logic, USA) |
12:30
- 14:00 Luncheon
14:00
- 15:00 Report on Breakout Sessions
15:15
- 23:00 Social Event
WEDNESDAY
May 28, 2003
8:30 - 10:00 Session 6A Scan and Core Testing
Moderators:
P.
Muhmenthaler (Infineon Technologies, D), M. Hirech (Synopsys, USA)
6A.1 |
Statistical
Diagnosis for Transient Scan Chain Hold-Time Fault
Y. Huang, W.-T. Cheng (Mentor Graphics, USA), S.M. Reddy (University of
Iowa, USA), C.-J. Hsieh, Y.-T. Hung (Faraday Technology, Taiwan)
|
6A.2 |
Efficient
Scan Chain Design for Power Minimization During Scan Testing Under Routing
Constraint
Y. Bonhomme, P. Girard (LIRMM, F), L. Guiller (Synopsys, USA), C.
Landrault, S. Pravossoudovitch (LIRMM, F) |
6A.3 |
Enhanced
P1500 Compliant Wrapper Suitable for Delay Fault Testing of Embedded Cores
H.J. Vermaak (Technikon Free State, SA & University of Twente, NL),
H.G. Kerkhoff (University of Twente, NL) |
8:30
- 10:00 Session 6B RF, EME, and Probing
Moderators:
B.
Straube (Fraunhofer IIS, D), H. Manhaeve (QStar, B)
6B.1* |
RF
ATE Equipment Benefit from Advanced Network Analyzer Technology
M. Seth, J. Lukez (Credence Europe, D)
|
6B.2* |
Characterization
of the EME of Integrated Circuits With the Help of the IEC Standard 61967
T. Ostermann (University of Linz, A), B. Deutschmann
(austriamicrosystems, A) |
6B.3* |
Probing
10 kV and 100 A: Challenges and Solutions for High Voltage / High Current
Wafer Testing
R. Gaggl (T.I.P.S. Messtechnik, A) |
10:00
- 11:00 Poster Session 4
Moderators:
B.
Rouzeyre (LIRMM, F), A. Paschalis (University
of Athens, GR)
P4.1 |
Test
Pattern De/Compaction for SoC Test in a Test Processor
Environment
C. Galke, M. Grabow, H. T. Vierhaus (Brandenburg University of
Technology, D)
|
P4.2 |
Automatic
Design of Cellular Automata for Generating Deterministic Test Patterns
T. Pikula, E. Gramatova, M. Fischerova (Slovak Academy of Sciences, SLO) |
P4.3 |
On
SAT-applicability to High-level Testing
E. Coltro, A. Fin, F. Fummi (University of Verona, I) |
P4.4 |
System
Verification Based on Modified Interval Analysis
I. Ugarte, P. Sanchez (University of Cantabria, E) |
P4.5 |
A
Macro-Based Instruction Level CPU Testing with an ADL
E. Safi, Z. Karimi, M. Abbaspour, Z. Navabi (University of Tehran, IR) |
P4.6 |
High
Level Input Stimuli Generation for Testing Hardware/Software System
O. Goloubeva, M. Sonza Reorda, M. Violante (Politecnico di Torino, I) |
P4.7 |
Concurrent
Optimisation of Self-Testable Designs from Behavioural Descriptions by a
Controller based Estimation Technique
M.S. Gaur, M. Zwolinski, B.M. Al-Hashimi (University of Southampton,
UK) |
11:00
- 12:30 Session 7A Delay Testing
Moderators:
W.-T.
Cheng (Mentor Graphics, USA), B. Becker (University
of Freiburg, D)
7A.1 |
On
Path Selection for Delay Fault Testing Considering Operating Conditions
B. Seshadri, I. Pomeranz (Purdue University, USA), S.M. Reddy
(University of Iowa, USA), S. Kundu (Intel, USA)
|
7A.2 |
A
Path Delay Test Generation Method for Sequential Circuits Based on
Reducibility to Combinational Test Generation
T. Iwagaki, S. Ohtake, H. Fujiwara (Nara Institute of Science and
Technology, J) |
7A.3 |
Requirements
for Delay Testing of Look-Up Tables in SRAM-Based FPGAs
P. Girard, O. Héron, S. Pravossoudovitch, M. Renovell (LIRMM, F) |
11:00
- 12:30 Session 7B Exploiting 1149.1 for Debug and Core Test
Moderators:
B.
Bennetts (Bennetts
Associates, UK),
B.
Sutton (Teradyne, D)
7B.1* |
Debug
Architecture for System on Chip Taking Full Advantage of the Test Access
Port
E. Moerman, S. Bocq, J. Verfaillie (Alcatel Bell, B)
|
7B.2* |
Using
JTAG for Design Debug on a System
L. van de Logt, F. van der Heyden, T. Waayers (Philips Research, NL) |
7B.3* |
An
Improved Test Control Architecture for Core-Based System Chips
T. Waayers (Philips Research, NL) |
12:30
- 14:00 Luncheon
14:00
- 15:30 Session 8 (Plenary) Test Data Compression
Moderators:
J.
Rajski (Mentor
Graphics, USA), M.
Sonza Reorda (Politecnico di Torino, I)
8A.1 |
A
Variable Length Continuous-Flow Scan Vector Decompression Scheme
C.V. Krishna, N.A. Touba (University of Texas at Austin, USA)
|
8A.2 |
On
Reducing Test Data Volume and Test Application Time for Multiple Scan
Chain Designs
H. Tang, S.M. Reddy (University of Iowa, USA), I. Pomeranz (Purdue
University, USA) |
8A.3* |
ATPG
Padding and ATE Vector Repeat for Reducing Test Data Volume
H. Vranken (Philips Research, NL), F. Hapke, S. Rogge (Philips
Semiconductors, D), D. Chindamo (Agilent Technologies, I), E. Volkerink
(Agilent Technologies, USA) |
15:30
- 15:40 CLOSING SESSION (Plenary)
*
Sessions and Papers in ETW’s Applications Track.
|