ETW'03
Tutorials
ETW’03
offers two full-day TTEP
2003 tutorials on May 25.
Testing
(Embedded) Memories: New Fault Models, Tests, DfT, BIST, BISR, and Industrial
Results,
by Ad J. van de Goor (Delft University of Technology).
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Intended
audience: Memory and ASIC designers, test algorithm and program
developers, researchers and managers of systems using (embedded) memories.
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Summary: This
tutorial addresses the more advanced topics of testing memories. SPICE
simulation of defects inserted into the electrical designs of SRAMs and
DRAMs is used to show the value of current fault models and to establish
many new fault models. The likelihood of the modeled faults is determined,
based on SPICE simulation and Inductive Fault Analysis. The space of all
functional faults is shown; it indicates the existence of many new
functional faults. Traditional tests, such as SCAN, Checkerboard, GALPAT,
and Walking 1/0 are covered, followed by the conventional march tests, such
as MATS+, March C-, MOVI, etc., and the new march tests for several of the
new fault models; their effectiveness will be illustrated, using industrial
test data. The intra-word coupling fault model, specific for word-oriented
memories, will be introduced together with an optimal set of data
backgrounds and a test approach for detecting those faults. Fault models,
specific for two-port memories, based on the notion of combinations of weak
faults, their probability of occurrence, and two tests are derived. A good
portion of the time is devoted to DfT, BIST, and BISR techniques; industrial
examples are used to illustrate the most important concepts. Last, a method
for designing an optimal set of tests for high volume products, such as
microprocessors and commodity SRAMs and DRAMs, will be presented, based on
the industrial evaluation of a large set of tests, applied to a large set of
DRAM chips, whereby an extensive set of stress combinations (such as address
orders, data backgrounds, voltage and temperature stresses) are used.
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Keywords: Defects, SPICE simulation, inductive fault analysis, fault models,
weak faults, March tests,
addressing schemes, data backgrounds, word-oriented memories, two-port
memories, stresses.
Defect-Oriented
Testing, by Peter Maxwell
(Agilent Technologies) and Rob Aitken (Artisan Components).
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Intended
audience: Design, test and manufacturing engineers and managers,
students and professors who would like to learn more about defect-oriented
testing.
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Summary:
The goal of this tutorial is to expose attendees to the concepts of
defect-oriented testing at a level which will both enable rapid
implementation and provide insights to assist in improving and extending the
methods into future designs and technologies. The tutorial starts with an
overview of defect-oriented testing, describes the physical characteristics
and electrical effects of CMOS IC defects and failure mechanisms, and shows
methods that can be effective in detecting them. The need for fault models
is discussed, and model validation and test generation processes are
identified. It is shown how to apply defect-oriented test in production, and
what the benefits are of the defect-oriented test strategy in improving
product quality and lowering cost. Finally, future trends in CMOS
technologies are examined and nanotechnologies are explored as a potential
alternative, describing defects and test approaches.
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Keywords:
defect-oriented test, realistic fault models, non-standard test
techniques, iddq testing, VLV testing, nanotechnologies
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