Commercial
tools for RTL Design-for-Test exist but how good are they?
Organizer:
Erik LARSSON (Linköpings
University - Sweden)
Moderator:
Nicola
NICOLICI (McMaster University -
Canada)
Abstract: Design
for
Testability on RT-level descriptions has been extensively explored by
academia
as a research domain in the past decade, and now commercial tools are
finally
on the market, and start to be used in industrial design flows. The
panel aims
at gathering different opinions on these tools and on their future
evolution:
are they welcome from industry? How much are they effective? How well
do they
fit in the existing design flows? Which are the expectations for new
techniques
and tools? What is likely feasible, and what is simply a
dream?
Panelists:
»
Chouki
AKTOUF (DeFacTo Technologies - France),
»
Wu-Tung
CHENG (Mentor Graphics Corp.
- USA),
»
Prab
VARMA (BluePearl Software - USA),
»
Kewal
SALUJA (University
of Wisconsin-Madison - USA),
»
Matteo
SONZA REORDA (Politecnico di
Torino - Italy),
Abstract: Semiconductor
process technologies continue
to scale down, and hence become more sensitive for even the smallest
disturbances. In addition, new transistor designs and the introduction
of
exotic new materials cause new, unfamiliar defect modes. And as design
complexity grows, there are more potential locations for failure.
Despite all
these trends, it seems that customers are only increasing their
expectations
with respect to product quality. Design-for-Yield is a popular
buzzword, but
right now, test is still needed to help us meet these quality
requirements. Can
the test community keep up with the fast-forward mode of process
technology and
design? What is the best test approach now, and in the future, and does
self-healing play a role in that? Will only companies that invest
heavily in
advanced test methods survive? Or is fault-tolerance our
future?
NASA
Flatsats: Spacecraft Testbeds for Mission
Success
Organizer:
Michael
WRIGHT (NASA - USA)
Moderator:
Yervant
ZORIAN (Virage
Logic – USA)
Abstract: This
special session
will address electronics testbeds (“flatsats”) that
have been developed by NASA
Goddard Space Flight Center (GSFC) for testing spacecraft avionics and
software. Flatsats from a range of “in-house”
flight projects will be
discussed, representing past and current missions: Lunar Reconnaissance
Orbiter
(LRO), Solar Dynamics Observatory (SDO), Space Technology -5 (ST-5),
and
Microwave Anisotropy Probe (MAP). The session will consist of brief
presentations on the flatsat concept and descriptions of each project,
followed
by a question-and-answer period. Topics to be presented include:
mission
overview, purpose and requirements of the flatsat system, functional
description, benefits to respective projects, and any lessons learned.
Abstract: Pre-silicon
verification
methods work with
models of the design and are therefore limited by the inherent
trade-off
between their accuracy and the associated simulation time. Designs are
sent to
fabrication when the confidence level seems high enough; unfortunately,
it
still happens that functional and electrical design errors remain
undetected in
pre-silicon verification and slip through to prototype silicon. Errors
that
slip through require fixing as soon as possible once detected on the
prototype.
Hence, the pre-silicon verification transitions to post-silicon
validation and
debug upon return of first silicon samples from the factory. The
continued need
for more effective and efficient debugging methods and instruments is
expected
to drive innovative and new debug research over the forthcoming years.
In this
tutorial, we present the fundamentals of this field, as well as give an
overview
of some recent advances in debug research and development. Topics to be
covered
include functional/electrical design errors, run-stop debugging,
real-time
functional observability, embedded instrumentation, integrated logic
analysis,
transaction-based debug, and integrated hardware/software debug. This
tutorial
is intended to stimulate people into starting research and development
work in
this exciting field.
Speakers:
»
Bart
VERMEULEN (NXP
Semiconductors – The Netherlands),
Update: the
P1687
(IJTAG) Hardware Proposal for Efficient Embedded Instrument Access,
Bandwidth,
and Connectivity – the ABC’s of Embedded Content
Moderator:
Rob
AITKEN (ARM – USA)
Abstract: Modern
ICs have achieved a level of complexity
where simple ATE test is not enough to determine if the part was
designed and
manufactured correctly – and modern packaging such as known
good die and
stacked die severely complicate the embedded landscape. More and more
ICs are including
Functional configuration choices; Debug logic (DFD); Test logic (DFT);
manufacturing process and environment monitors (DFM); and
yield-analysis
support logic (DFY) – these logics need to be accessed at
wafer probe, at
package test, at board test, and even in-system. In the past, this
logic was
usually targeted at only one use environment and with ad hoc
consideration for
access – today these logics must interact with each other and
they require
formal scheduling and cataloguing to enable access, configuration, and
operation that will fit within engineering budgets, cost and time
budgets, and
test equipment resource budgets. This embedded tutorial will show the
multiple
defined instrument interfaces to meet the access needs of various
instruments;
the connection schemes that can be applied versus engineering budgets
such as
area, routing, power, and access efficiency; the proposed
high-bandwidth data
connections that will allow high data-volume, targeted instrument
latency, and
instrument-to-instrument communication; and how all of this falls
within the
operating arena of the 1149.1 JTAG TAP and TAP Controller.
DFT/BIST
Circuit
Techniques Using Sigma-Delta Encoding Methods
Moderator:
Adam
OSSEIRAN (Edith Cowan University – Australia)
Abstract: This
tutorial will look at different ways in which
sigma-delta techniques can be used for DFT and BIST. One section will
describe
varous methods in which to generate high-precision analog signals, such
as DC,
sinusoids, multi-tones, Gaussian noise signals, phase and frequency
modulated
signals, etc. Such methods have application for retrofitting digital
testers as
mixed-signal testers, as well as extending the capability of existing
mixed-signal testers. Subsequently, we’ll demonstrate how
sigma-delta methods
can be used in a wide range of DFT/BIST circuits for SOC applications.
This
will include signal sources, digitizers, coherent samplers, time-domain
reflectometry
and transmission, and noise and jitter analyzers.
Reliability,
Availability and
Serviceability of Networks-on-Chip
Moderator:
Gert Jervan (TallinnUniversity of Technology
– Estonia)
Abstract: This
tutorial presents an overview of the issues related to
the test, diagnosis and fault-tolerance of NoC-based systems. First,
the
characteristics of the NoC design (topologies, structures, routers,
wrappers,
and protocols) are presented, as well as a summary of the terms used in
the
field and an overview of the existing industrial NoCs is given. Then,
the challenges
to test, diagnose and tolerate faults in a NoC-based system are
discussed.
Current test strategies are then presented: re-use of on-chip network
for core
testing, test scheduling for the NoC reuse, test access methods and
interface,
efficient re-use of the network, and power-aware and thermal-aware
testing. In
addition, the challenges and solutions for the NoC (interconnects,
routers, and
network interface) test and diagnosis are presented. Finally, since
quality-of-service is one of the main challenges for the NoC use, fault
tolerance techniques for the NoC are discussed.
Abstract: Representatives
of large national and international joint
research projects in the area of test will share their experiences. The
benefits and the technical results, the added value of joint research
and the
organisation and administration of large projects as well as the
presentation
and evaluation of the research results will be discussed. Furthermore,
topics
and possibilities of future joint projects will be investigated under
both
technical and organizational aspects.
Speakers:
»
Kees VEELENTURF
(NANOTEST, NXP – The Netherlands)
»
Sybille HELLEBRAND
(REALTEST, University
of Paderborn
- Germany)
»
Andrew RICHARDSON
(NoE Patent-DfMM, University
of Lancaster
- UK)
