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Symposium booklet is now avalaible
Invited Distinguished Speaker from Group of Dr. Albert FERT, Nobel Prize Laureate in Physics, 2007. See the DETMET program here
ETS on-line registration is now closed. Only on-site registration will be possible, starting from Monday, May 27th, at 13h00.
Presentation slides in ppt format must be uploaded though the MOLE System web site before May 20, 2013
Final Technical Program
You can download the symposium booklet in PDF format by clicking here.
The Program At a Glance in PDF format is available here.
Monday, May 27, 2013
14:00-18:30 EMBEDDED TUTORIALS
14:00-18:30 Tutorial 1 (ROOM: CHAMBRE DU TRÉSORIER)
Effective Post-Silicon Validation
Subhasish Mitra (Stanford University, US)
14:00-18:30 Tutorial 2 (ROOM: PANETERIE)
Design, Test and Debug of Printed Circuit Assemblies
Bill Eklow and Brice Achkir (Cisco Systems, US)
19:00-20:30 WELCOME RECEPTION (ROOM: PANETERIE)
Tuesday, May 28, 2013
8:30-10:30 SESSION 1: PLENARY OPENING (ROOM: CELLIER BENOIT XII)
8:30-9:00 Opening Ceremony
Welcome Address
Patrick Girard (LIRMM, FR), ETS’13 General Chair
Program Introduction
Zebo Peng (Linköping University, SE), ETS’13 Program Chair
Symposium Information
Arnaud Virazel (LIRMM, FR), ETS’13 Organization Chair
ETS’12 Best Paper Award
Bernd Becker (University of Freiburg, DE), ETS’12 Vice-Program Chair
9:00-9:45 Keynote 1
Magical Thinking Applied to Test Engineering Reality (and vice versa)
Jeff Rearick, AMD, USA
9:45-10:30 Keynote 2
Outlook for Many-Core Systems: Cloudy with a Chance of Virtualization
Nikil Dutt, UC Irvine, USA
10:30-11:00 COFFEE BREAK (ROOM: PANETERIE)
11:00-12:30 SESSIONS 2A, 2B, 2C
Session 2A (ROOM: CELLIER BENOIT XII)
Testing of Core-based SOCs and 3-D stacked IC
Moderators: Janusz Rajski (Mentor Graphics, US), Sandeep K. Goel (TSMC, US)
2A.1- Robust Optimization of Test-Architecture Designs for Core-Based SoCs
Sergej Deutsch, Krishnendu Chakrabarty (Duke University, US)
2A.2- Computing Detection Probability of Delay Defects in Signal Line TSVs
Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel (LIRMM, FR); Pascal Vivet, Marc Belleville (CEA-LETI, FR)
2A.3- Automated DfT Insertion and Test Generation for 3D-SICs with Embedded Cores and Multiple Towers
Christos Papameletis, Brion Keller, Vivek Chickermane (Cadence Design Systems, NL); Erik Jan Marinissen (IMEC, BE); Said Hamdioui (Delft University of Technology, NL)
Session 2B (ROOM: CHAMBRE DU TRESORIER)
Software-based Test and System Dependability
Moderators: Dimitris Gizopoulos (University of Athens, GR), Michael Nicolaidis (TIMA, FR)
2B.1- Efficient Fault Simulation through Dynamic Binary Translation for Dependability Analysis of Embedded Software
Graziano Pravadelli, Franco Fummi (University of Verona, IT); Giuseppe Di Guglielmo (Columbia University in the City of New York, US); Davide Ferraretto (University of Verona, IT)
2B.2- Experimental Evaluation of Thread Distribution Effects on Multiple Output Errors in GPUs
Paolo Rech, Caroline Aguiar (UFRGS, BR); Christopher Frost (STFC, UK); Luigi Carro (UFRGS, BR)
2B.3- A Software-Based Self Test of CUDA Fermi GPUs
Daniele Rolfo, Stefano Di Carlo, Giulio Gambardella, Marco Indaco, Ippazio Martella, Paolo Prinetto, Pascal Trotta (Politecnico di Torino, IT)
Session 2C Special Industrial Session (ROOM: PANETERIE)
Designing and Manufacturing Zero-Defect-per-Million ICs in Forthcoming Technologies
Moderators: Bernard Courtois (CMP, FR), Haralampos Stratigopoulos (TIMA, FR)
2C.1- Diagnostic for Yield and Reliability Learning: Industrial Experiences
Davide Appello, STMicroelectronics, IT
2C.2- Process Technology, Test and Zero Defects
Bram Kruseman, NXP, NL
2C.3- Zero Defect – More than Fault Coverage and Fault Models
Hermann Obermeir, Infineon, DE
12:30-14:15 LUNCH (ROOM: ESPACE JEANNE LAURENT)
14:15-15:45 SESSIONS 3A, 3B, 3C
Session 3A (ROOM: CELLIER BENOIT XII)
Scan-based Test and Diagnosis
Moderators: John P. Hayes (University of Michigan, US), Bruno Rouzeyre (LIRMM, FR)
3A.1- Scan Pattern Retargeting and Merging with Reduced Access Time
Rafal Baranowski, Michael Kochte, Hans-Joachim Wunderlich (University of Stuttgart, DE)
3A.2- Utilizing Circuit Structure for Scan Chain Diagnosis
Lo Wei-Hen, Hsieh Ang-Chih, Lan Chien-Ming, Lin Min-Hsien, Hwang Tingting (National Tsing Hua University, TW)
3A.3- A Layout-aware X-Filling Approach for Dynamic Power Supply Noise Reduction in At-Speed Scan Testing
Saman Kiamehr, Farshad Firouzi, Mehdi Tahoori (Karlsruhe Institute of Technology, DE)
Session 3B Workshop-Type Papers (ROOM: CHAMBRE DU TRESORIER)
Low-Power Scan, JTAG and Defect Simulation
Moderators: Joan Figueras (UPC, ES), Xiaoqing Wen (Kyushu Institute of Technology, JP)
3B.1- Peak scan capture power reduction using a novel on-chip clock sequencer
Swapnil Bahl, Shray Khullar (STMicroelectronics, IN)
3B.2- A New Execution Model for Interactive JTAG Applications
Michele Portolan, Bradford Van Treuren, Suresh Goyal (Alcatel-Lucent, US)
3B.3- A new analog defect simulator, using old techniques
Stephen Sunter (Mentor Graphics, DE); Krzysztof Jurga, Bartosz Kaczmarek (Poznan University, PL)
Session 3C Vendor Presentation Session (ROOM: PANETERIE)
Test and Reliability Improvement
Moderators: Sule Ozev (Arizona State University, US), Wu-Tung Cheng (Mentor Graphics, US)
3C.1- T2000 IPS Effective Test Solution for Integrated Power Devices
Stuart AINSLIE (Advantest Europe, GmbH)
3C.2- Embedded Test and Repair for Advanced Geometry Designs
Yervant Zorian, (Synopsys, USA)
3C.3- Ridgetop Innovations for Improved Testing, Better Reliability, and Foundry Process Qualification
Hans Manhaeve (Ridgetop Europe, BE)
15:45-16:45 POSTERS & COFFEE BREAK (ROOM: PANETERIE)
POSTER SESSION P1 - Fault Tolerance, Diagnosis, and Reliability
P1.1- Fault mitigation strategies for CUDA GPUs
Daniele Rolfo, Stefano Di Carlo, Giulio Gambardella, Marco Indaco, Ippazio Martella, Paolo Prinetto, Pascal Trotta (Politecnico di Torino, IT)
P1.2- Variability-Aware and Fault-tolerant Self-Adaptive applications for Many-Core chips
Fabien Chaix, Gilles Bizot, Michael Nicolaidis, Zergainoh Nacer-Eddine (TIMA, FR)
P1.3- A Minimum MSE Sensor Fusion Algorithm with Tolerance to Multiple Faults
Omid Sarbishei, Atena Roshan Fekr, Majid Janidarmian, Benjamin Nahill, Katarzyna Radecka (McGill University, CA)
P1.4- Bias Temperature Instability Analysis in SRAM Decoder
Seyab Khan, Said HamdiouiI (Delft University of Technology, NL); Halil Kukner, Praveen Raghavan, Francky Catthoor (IMEC, BE)
P1.5- Generation of Compact Multi-Cycle Diagnostic Test Sets
Irith Pomeranz (Purdue University, US)
P1.6- Aggresive Scan Chain Masking for Improved Diagnosis of Multiple Scan Chain Failures
Subhadip Kundu, Santanu Chattopadhyay, Indranil Sen Gupta (Indian Institute of Technology Kharagpur, IN); Rohit Kapur (Synopsys, US)
P1.7- PinPoint: An Algorithm for Enhancing Diagnostic Resolution Using Capture-Cycle Power Information
Seetal Potluri (Indian Institute of Technology Madras, IN); Satya Trinadh (Indian Institute of Technology Hyderabad, IN); Roopashree Baskaran (National Institute of Technology Trichy, IN), Kamakoti Veezhinathan, Nitin Chandrachoodan (Indian Institute of Technology Madras, IN)
16:45-18:15 SESSIONS 4A, 4B, 4C
Session 4A (ROOM: CELLIER BENOIT XII)
Analog and RF Test 1
Moderators: Abhijit Chatterjee (Georgia Tech, US), Emmanuel Simeu (TIMA, FR)
4A.1- Adaptive Quality Binning for Analog Circuits
Ender Yilmaz, Sule Ozev (Arizona State University, US); Kenneth Butler (Texas Instruments, US)
4A.2- On Combining Alternate Test with Spatial Correlation Modeling in Analog/RF ICs
Ke Huang (University of Texas at Dallas, US); Nathan Kupp (Yale University, US); John Carulli (Texas Instruments, US); Yiorgos Makris (University of Texas at Dallas, US)
4A.3- M-S Test Based on Specification Validation Using Octrees in the Measure Space
Alvaro Gomez-Pau, Luz Balado, Joan Figueras (UPC, ES)
Session 4B - Panel (ROOM: CHAMBRE DU TRESORIER)
What is the Electronics Industry Doing to Win the Battle Against the Expected Scary Failure Rates in Future Technology Nodes?
Organizer and Moderator: Said Hamdioui (Delft University of Technology, NL)
Panelists:
Davide Appello (STMicroelectronics, IT)
Arnaud Grasset (Thales, FR)
Xinli Gu (Huawei, US)
Bram Kruseman (NXP, NL)
Riccardo Mariani (YogiTech, IT)
Hermann Obermeir (Infineon, DE)
Srikanth Venkataraman (Intel, US)
Session 4C (ROOM: PANETERIE)
EU Project Information 1
Moderators: Dan Alexandrescu (iRoC Technologies, FR), Mohamed Azimane (NXP Semiconductors, NL)
4C.1- FP7 DIAMOND: Design Error Diagnosis and Correction Success Stories
Jaan Raik, Maksim Jenihhin (Tallinn University of Technology, EE); Robert Könighofer, Georg Hofferek (Graz University of Technology, AT); Alexander Finder, Görschwin Fey (University of Bremen, DE)
4C.2- AUTOMICS: A Novel Approach for Substrate Modeling for Automotive Applications
Ramy Iskander (LIP6, FR)
4C.3- TRUDEVICE: A COST Action on "Trustworthy Manufacturing and Utilization of Secure Devices"
Giorgio Di Natale (LIRMM, FR)
18:30-19:30 Wine Testing Party (ROOM: PANETERIE)
Wednesday, May 29, 2013
8:30-10:00 SESSIONS 5A, 5B, 5C
Session 5A (ROOM: CELLIER BENOIT XII)
Analog and RF Test 2
Moderators: Jacob Abraham (University of Texas at Austin, US), Herbert Eichinger (Infineon, AU)
5A.1- Analytical Modeling for EVM in OFDM Transmitters Including the Effects of IIP3, I/Q imbalance, Noise, AM/AM and AM/PM Distortion
Afsaneh Nassery, Sule Ozev (Arizona State University, US); Mustapha Slamani (IBM, US)
5A.2- Efficient selection of signatures for analog/RF alternate test
Manuel Barragan, Gildas Leger (IMSE-CNM, ES)
5A.3- Efficient System-Level Testing and Adaptive Tuning of MIMO-OFDM Wireless Transmitters
Shyam Kumar Devarakond, Debashis Banerjee, Aritra Banerjee (Georgia Institute of Technology, US); Shreyas Sen (Intel, US); Abhijit Chatterjee (Georgia Institute of Technology, US)
Session 5B - Workshop-Type Papers (ROOM: CHAMBRE DU TRESORIER)
Security, Safety and Yield Analysis
Moderators: Paolo Prinetto (Politecnico di Torino, IT), Regis Leveugle (TIMA, FR)
5B.1- #SAT for Vulnerability Analysis of Security Components
Linus Feiten, Matthias Sauer, Tobias Schubert, Alexander Czutro (University of Freiburg, DE); Victor Tomashevich (University of Passau, DE); Eberhard Boehl (Robert Bosch GmbH, DE); Ilia Polian (University of Passau, DE); Bernd Becker (University of Freiburg, DE)
5B.2- Verification Tool Development in Accordance with ISO 26262
Daniel Carlsson, Urban Ingelsson, Viacheslav Izosimov (Semcon, SE)
5B.3- Industrial Practice for Diagnosis Driven Yield Analysis (DDYA)
Wu Yang, Yu Huang (Mentor Graphics, US)
Session 5C - Special Industrial Session (ROOM: PANETERIE)
Updates and Advanced Practices from EDA Vendors
Moderators: Oliver Bringmann (Eberhard-Karls-University of Tuebingen, DE), Maria K. Michael (University of Cyprus, CY)
5C.1- Cell-aware Production Test Results from a 350nm Automotive Design
Friedrich Hapke (Mentor, DE); Marek Hustava (On Semiconductor, CZ)
5C.2- EDA Powering the Future in IC Test
Rohit Kapur (Synopsys, US)
5C.3- Smartscan - Reduced Pin Count Compression with Low Power Advantages- Ideal for Mixed Signal Designs
Krishna Chakravadhanula, Vivek Chickermane, Don Pearl, Subhasish Mukherjee, Robert Asher, Rajesh Khurana, Yogyata Thareja, Bassilios Petrakis (Cadence, US)
10:00-11:00 POSTERS & COFFEE BREAK (ROOM: PANETERIE)
POSTER SESSION P2
Analog/RF and 3D IC Test, Fault Simulation and Test Generation
P2.1- Efficient minimization of test frequencies for linear analog circuits
Mohand Bentobache (University of Bejaia, DZ); Ahcene Bounceur, Reinhardt Euler (Lab-STICC, FR); Yann Kieffer (LCIS, FR); Salvador Mir (TIMA, FR)
P2.2- Implementing model redundancy in predictive alternate test to improve test confidence
Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Olivier Potin, Michel Renovell (LIRMM, FR)
P2.3- RF BIST and Test Strategy for the receive part of an RF Transceiver in CMOS technology
Christophe Kelma, Sebastien Darfeuille, Andreas Neuburger, Andreas Lobnig (NXP, FR)
P2.4- Hybrid 3D Pre-bonding Test Framework Design
Unni Chandran (Intel, US); Danella Zhao (University of Louisiana at Lafayette, US); Rathish Jayabharathi (Intel, US)
P2.5- BIST Architecture to Detect Defects in TSVs During Pre-Bond Testing
Daniel Arumi, Rosa Rodriguez-Montanes, Joan Figueras (UPC, ES)
P2.6- Test Generation for Circuits with Embedded Memories Using SMT
Sarvesh Prabhu, Michael Hsiao (Virginia Tech, US); Loganathan Lingappan, Vijay Gangaram (Intel, US)
11:00-12:30 SESSIONS 6A, 6B, 6C
Session 6A (ROOM: CELLIER BENOIT XII)
Computational Approaches to Test
Moderators: Adit Singh (Auburn University, US), Jerzy Tyszer (Poznan University of Technology, PL)
6A.1- Information-Theoretic Syndrome And Root-Cause Analysis For Guiding Board-Level Fault Diagnosis
Fangming Ye (Duke University, US); Zhaobo Zhang (Huawei Technologies, US); Krishnendu Chakrabarty (Duke University, US); Xinli Gu (Huawei Technologies, US)
6A.2- A Mutual Characterization Based SAR ADC Self-Testing Technique
Hao-Jen Lin (National Taiwan University, TW); Xuan-Lun Huang (ITRI, TW), Jiun-Lang Huang (National Taiwan University, TW)
6A.3- Extracting Device-Parameter Variations using a Single Sensitivity-Configurable Ring Oscillator
Yuma Higuchi, Ken-ichi Shinkai, Masanori Hashimoto (Osaka University, JP); Rahul Rao, Sani Nassif (IBM, US)
Session 6B - Panel (ROOM: CHAMBRE DU TRESORIER)
Current Testing: Dead or Alive?
Organizer: Hans MANHAEVE (Ridgetop Europe, BE)
Moderator: Pete Harrod (ARM, UK)
Panelists:
Hans Manhaeve (Ridgetop Europe, BE)
Adit Singh (Auburn University, US)
Chintan Patel (UMBC, US)
Ralf Arnold (Infineon, DE)
Davide Appello (STMicroelectronics, IT)
Session 6C (ROOM: PANETERIE)
EU Project Information 2
Moderators: Michel Renovell (LIRMM, FR), Liviu Miclea (Technical University of Cluj-Napoca, RO)
6C.1- RELY – Design for Reliability of SoCs
Domenik Helms, Reef Eilers, Frank Oppenheimer (OFFIS Institute for Information Technology, DE); Wolfgang Nebel (University of Oldenburg, DE)
6C.2- Towards on-Demand System Reliability: Software Implemented Fault Tolerance and Testing
Ioannis Sourdis (Chalmers University of Technology, SE); Rishad A. Shafik (Bristol University of Technology, UK); Christos Strydis (Neurasmus B.V., NL); Dionisios Pnevmatikatos, Dimitris Theodoropoulos (Foundation for Research and Technology, GR); Dhiraj K. Pradhan (Bristol University of Technology, UK); Gerard K. Rauwerda (Recore Systems B.V., NL)
6C.3- MASTER_3D: Manufacturing Solutions Targeting Competitive European Production in 3D
Brigitte Descouts (STMicroelectronics, FR)
12:30-14:00 LUNCH (ROOM: ESPACE JEANNE LAURENT)
14:00-15:00 SESSIONS 7A, 7B, 7C
Session 7A - Embedded Tutorial (ROOM: CELLIER BENOIT XII)
Moderator: Danella Zhao (University of Louisiana at Lafayette, US)
Reconciling the IC Test and Security Dichotomy
Ozgur SinanogluI (New York University of Abu Dhabi, UAE), Ramesh Karri (Polytechnic Institute of New York University, US), Yiorgos Makris (University of Texas, Dallas, US)
Session 7B - Embedded Tutorial (ROOM: CHAMBRE DU TRESORIER)
Moderator: Sudhakar M. Reddy (University of Iowa, US)
Semiconductor Failure Modes and Mitigation for Critical Systems
Hans Manhaeve, Esko Mikkola (Ridgetop Europe, BE)
Session 7C - Embedded Tutorial (ROOM: PANETERIE)
Moderator: Ilia Polian (University of Passau, DE)
Approximate computing: an emerging paradigm for energy-efficient design
Jie Han (University of Alberta, CA), Michael Orshansky (University of Texas, Austin, US)
15:30-23:30 SOCIAL EVENT & DINNER
Thursday, May 30, 2013
8:30-10:00 SESSIONS 8A, 8B, 8C
Session 8A (ROOM: CELLIER BENOIT XII)
Memory Reliability and Repair
Moderators: Sybille Hellebrand (Paderborn University, DE), Nabil Badereddine (Intel Mobile Communications, FR)
8A.1- Error Correction Schemes with Erasure Information for Fast Memories
Valentin Gherman, Samuel Evain (CEA-LIST, FR)
8A.2- Reducing Power Dissipation in Memory Repair for High Defect Densities
Panagiota Papavramidou, Michael Nicolaidis (TIMA, FR)
8A.3- Analyzing Resistive-Open Defects in SRAM Core-Cell under the Effect of Process Variability
Elena Ioana Vatajelu, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel (LIRMM, FR); Nabil Badereddine (Intel, FR)
Session 8B (ROOM: CHAMBRE DU TRESORIER)
Phd Student Work-In-Progress Papers
Moderators: Alex Bystrov (Newcastle University, UK), Paolo Bernardi (Politecnico di Torino, IT)
8B.1- Towards a New Approach for Handling Hard Faults in Register Files by Means of a Software-Based Register Re-Allocation
Sebastian Mueller, Mario Schoelzel, Heinrich VierhausI (BTU Cottbus, DE)
8B.2- A New Method for Control Flow Error Detection Using the Debug Interface
Du Boyang, Matteo Sonza Reorda, Luca Sterpone (Politecnico di Torino, IT)
8B.3- Modular Test Framework: From Component Test to Production Test
Kristian Trenkel, Ulrich Heinkel (Chemnitz University of Technology Commitment, DE); Jörg Tremmel, Florian Spiteller (iSyst Intelligente Systeme GmbH, DE)
Session 8C - Vendor Presentation Session (ROOM: PANETERIE)
Advanced Test Solutions
Moderators: Mehdi Tahoori (Karlsruhe Institute of Technology, DE), Paul-Henri Pugliesi Conti (NXP, FR)
8C.1- Cost-Effective Partial Scan Automation at RTL
Julien Pouget, Chouki Aktouf (DeFacTo Technologies, FR)
8C.2- ATE Solutions to 3D-IC Test Challenges
Scott Chesnut, Bob Smith, Cros Florent, Nambur Lakshmikanth (Advantest, US)
8C.3- Creating Structural Patterns for At-speed Testing
Teresa McLaurin (ARM, US)
10:00-11:00 POSTERS & COFFEE BREAK (ROOM: PANETERIE)
POSTER SESSION P3
Workshop-type/Work-in-Progress/EU-project Information
P3.1- Design and Performance Characteristics for 10 Gbps Burst-Mode Clock/Data Recovery
David Keezer, Carl Gray (Georgia Institute of Technology, US)
P3.2- Visualization and Debug of Topological Quantum Computers
Alexandru Paler (University of Passau, DE); Simon Devitt, Kae Nemoto (National Institute of Informatics Tokyo, JP); Ilia Polian (University of Passau, DE)
P3.3- RTN Variation Tolerant Screening Test Using Accelerated Margin Shifts for Nano-Scaled SRAM
Worawit Somha, Hiroyuki Yamauchi (Fukuoka Institute of Technology, JP)
P3.4- Fault Management Instrumentation Network based on IEEE P1687 IJTAG
Konstantin Shibin, Artur Jutman, Sergei Devadze (Tallinn University of Technology, EE)
P3.5- Analog Measurements based on Digital Test Equipment for Low-Cost Testing of Analog/RF Circuits
Francois Lefevre (NXP, FR)
P3.6- Wireless Testing and Test Data Compression for Complex Systems: Demonstrator
Marie-Lise Flottes, Olivier Potin, David Andreu, Serge Bernard (LIRMM, FR); Philippe Cauvet (Ophtimalia SAS, FR); Paul-Henri Pugliesi Conti (NXP Semiconductors, FR)
11:00-12:30 SESSIONS 9A, 9B, 9C
Session 9A (ROOM: CELLIER BENOIT XII)
Low-Power Bist And Timing Issue
Moderators: Peter Maxwell (Aptina Imaging, US), Ozgur Sinanoglu (New York University in Abu Dhabi, UAE)
9A.1- New Test Compression Scheme Based on Low Power BIST
Jerzy Tyszer, Michal Filipek (Poznan University of Technology, PL); Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski (Mentor Graphics, US)
9A.2- Novel Approach to Reduce Power Droop During Scan-Based Logic BIST
Martin Eugenio Omana, Filippo Fuzzi, Daniele Rossi, Cecilia Metra (University of Bologna, IT); Chandra Tirumurti, Rajesh Galivanche (Intel, US)
9A.3- Optimization for Timing-Speculated Circuits by Redundancy Addition and Removal
Yuxi Liu, Rong Ye, Feng Yuan, Qiang Xu (The Chinese University of Hong Kong, HK)
Session 9B - Special Session (ROOM: CHAMBRE DU TRESORIER)
State-of-the-Art of Inter-domain Safety, Security and Fault Tolerance
Moderators: Gyorgy Kalman (ABB, NO), Viacheslav Izosimov (Semcon, SE)
9B.1- Functional Safety Trends in Automotive and Industrial Systems
Riccardo Mariani (Yogitech, IT)
9B.2- Benchmarking the Hardware Error Sensitivity of Executable Programs
Johan Karlsson (Chalmers University of Technology, SE)
9B.3- Reliability Analysis and Modelling for Complex Silicon Devices
Dan Alexandrescu (iRoC Technologies, FR)
9B.4- On the Practical Approaches to Consolidate Safety and Security in Critical Infrastructure
Mohammad Chowdhury (ABB, NO)
Session 9C - Vendor Presentation Session (ROOM: PANETERIE)
Process Characterization and Board Test
Moderators: Matteo Sonza Reorda (Politecnico di Torino, IT), Riccardo Mariani (Yogitech, IT)
9C.1- Rapid Characterization Method for New Semiconductor Processes
Hans Manhaeve (Ridgetop Europe, BE); Esko Mikkola, Andrew Levy (Ridgetop Group Inc., US)
9C.2- FPGA Assisted Test for Design Validation and Production Test
Jan Heiber (GOEPEL electronic GmbH, DE)
9C.3- IP Cores Based Test Technology for Electronic Boards
Patrice Deroux-Dauphin (Temento Systems, FR)
12:30-14:15 LUNCH (ROOM: ESPACE JEANNE LAURENT)
14:15-15:15 SESSIONS 10 (ROOM: CELLIER BENOIT XII)
Error and Threat Detection and Self-Repair
Moderators: Hans-Joachim Wunderlich (University of Stuttgart, DE), Lorena Anghel (TIMA, FR)
10.1- An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems
Matteo Sonza Reorda, Luca Sterpone, Anees Ullah (Politecnico Di Torino, IT)
10.2- Run-time Detection of Hardware Trojan: The Processor Protection Unit
Jérémy Dubeuf, David Hely (Grenoble INP, FR); Ramesh Karri (Polytechnic Institute of New York University, US)
15:15-15:45 CLOSING CEREMONY (ROOM: CELLIER BENOIT XII)
