|
| Poster Session P3: Scan and DFT | paper | |
|---|---|---|
| P3.1 | TACOS: A Testability Allocation
and Control System
L. Ducerf-Bourbon* - M. Marzouki* - P. Bukovjan** * LIP6 Laboratory, France ** ON Semiconductor, Czech Republic |
|
| P3.2 | A High Performance, Low Power,
Scan Element
L. Basto - D. Galbi Analog Devices, USA |
|
| P3.3 | Partial Scan Design Based
on Reachable States
T. Ohmameuda - H. Ito Chiba University, Japan |
|
| P3.4 | From Circuit Simulation to
Circuit Verification: An Internal + Boundary Scan-based Solution
M. Lubaszweski* - M.R. Krug* - G.R. Alves** - J.M. Martins Ferreira' * Federal University of Rio Grande do Sul, Brasil ** ISEP, Portugal ' FEUP, Portugal |
|
| P3.5 | An Efficient Deterministic
Test Pattern Compaction Scheme Using Modified IC Scan Chain
O. Novàk* - J. Hlavicka** * Technical University of Liberec, Czech Republic ** Czech Technical University, Czech Republic |
|
| P3.6 | On the Acceleration of BST-based
Monitoring Processes
J.M. Vieira dos Santos ISEP, Portugal |
|
|
