General Info


Test Spring School

Vendor Sessions

Local Information


Technical Program

You can download the program in iCal format by clicking here.

You can download the booklet here.

Monday, May 28

14:00-18:30 Tutorial 1 (Verdi A)

Title: Dependable Processor Design



14:00-18:30 Tutorial 2 (Berlioz AB)

Title: Hardware- and Software-Fault Tolerance, Design and Assessment of Dependable Computer Systems



Tuesday, May 29

8.30-9.00 Opening Session (Salle de l’Europe)

Welcome Address:Lorena Anghel (TIMA Laboratory)
ETS 2012 General Chair
Technical Program Overview:Massimo Violante (Politecnico di Torino)
ETS 2012 Program Chair
ETS 2011 Best Paper Award:Erik Larsson (Lund University)
ETS 2011 Program Chair

9.00-10.30 Keynote and Invited Presentation (Salle de l’Europe)

Keynote: Goldilocks Failures: Not Too Soft, Not Too Hard

Sani Nassif (IBM, USA)


Invited talk: Power-Aware Testing: The Next Stage

Xiaoqing Wen (Kyushu Institute of Technology, Japan)


10.30-11.30 Coffee Break and Poster Session (Foyer)

  • P1.1) Disturbance Fault Testing on Various NAND Flash Memories
    C.-S. Hou, J.-F. Li (National Central University)
  • P1.2) Functional Analysis of Circuits Under Timing Variations
    M. Dehbashi, G. Fey (University of Bremen), K. Roy, A. Raghunathan (Purdue University)
  • P1.3) Enhanced Wafer Matching Heuristics for 3-D ICs
    V. Pavlidis, H. Xu, G. De Micheli (EPFL)
  • P1.4) Defect Analysis in Power Mode Control Logic of Low-Power SRAMs
    L. Zordan, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Todri, A. Virazel (LIRMM), N. Badereddine (Intel)
  • P1.5) Coupling-Based Resistive-Open Defects in TAS-MRAM Architectures
    J. Azevedo, A. Virazel, A. Bosio, L. Dilillo, P. Girard, A. Todri (LIRMM), G. Prenat (CEA), J. Alvarez-Herault, K. Mackay (CROCUS Technology)

    11.30-12.30 Sessions 1

    Session 1A: Power-aware test (Ravel A)

    Moderator: Patrick Girard (LIRMM, FR)

  • 1A.1) DfT Support for Launch and Capture Power Reduction in Launch-Off-Capture Testing
    O. Sinanoglu (New York University - Abu Dhabi), S. Saeed (NYU-Poly)
  • 1A.2) Cost and Power Efficient Timing Error Tolerance in Flip-Flop Based Microprocessor Cores
    S. Valadimas (University of Athens), Y. Tsiatouhas (University of Ioannina), A. Arapoyanni (University of Athens)

    Session 1B: On-line SoC testing (Verdi A)

    Moderator: Dimitris Gizopoulos (U. Athens, GR)

  • 1B.1) Bandwidth-Aware Test Compression Logic for SoC Designs
    J. Tyszer (Poznan University of Technology), G. Mrugalski, J. Rajski (Mentor Graphics Corporation), J. Janicki (Poznan University of Technology)
  • 1B.2) On-Line Software-Based Self-Test of the Address Calculation Unit in RISC Processors
    P. Bernardi, M. Grosso, E. Sanchez, M. Sonza Reorda, L. Ciganda, J. Lagos, M. Carvalho (Politecnico di Torino), O. Ballan (STMicroelectronics)

    Session 1C (vendor): Embedded interfaces for test (Berlioz AB)

    Moderator: Liviu Miclea (Technical University of Cluj-Napoca, RO)

  • 1C.1) Embedded System Access for modern Test and Programming Strategies
    T. Wenzel, H. Ehrenberg, J. Heiber (GOPEL electronic)
  • 1C.2) JTAG and SVF: Interactive ATE Communication with Devices via Protocol Scripts
    M. Seuring (Advantest)

    12.30-14.30 Lunch

    14.30-16.00 Sessions 2

    Session 2A: Fault Tolerant FPGA-based systems (Ravel A)

    Moderator: Bruno Rouzeyre (LIRMM, FR)

  • 2A.1) Fast Error Detection through Efficient Use of Hardwired Resources in FPGAs
    G. Nazar, L. Carro (Universidade Federal do Rio Grande do Sul)
  • 2A.2) Increasing autonomous fault-tolerant FPGA-based systems' lifetime
    C. Sandionigi, A. Miele, C. Bolchini (Politecnico di Milano)
  • 2A.3) Fault Tolerant FPGA Processor Based on Runtime Reconfigurable Modules
    M. Psarakis, A. Apostolakis (University of Piraeus)

    Session 2B: Analog testing (Verdi A)

    Moderator: Joan Figueras (UPC, E)

  • 2B.1) BIST Design for Analog Cell Matching
    C. Duarte (INESC Porto), H. Cavadas, P. Coke, L. Malheiro (uSG FEUP), V. Tavares, P. Guedes De Oliveira (INESC Porto)
  • 2B.2) Enhanced Reduced Code Linearity Test Technique for Multi-bit/Stage Pipeline ADCs
    A. Laraba, H. Stratigopoulos, S. Mir (TIMA Laboratory), H. NAUDET, C. FOREL (STM)
  • 2B.3) Adaptive multi-site testing for analog/mixed-signal circuits incorporating neighborhood information
    E. Yilmaz, S. Ozev (Arizona State University), K. Butler (Texas Instruments)

    Special Session 2C: Project ELESIS, DIAMOND and Dependable Embedded Systems (Berlioz AB)

    Moderator: Dan Alexandrescu (IROCTECH, FR)

  • 2C.1) Reducing Test Cost for Mixed Signal Circuits "From TOETS to ELESIS". Read more...
    Mohamed Azimane (NXP Semiconductors, The Netherlands)
  • 2C.2) FP7 Collaborative Research Project DIAMOND: Diagnosis, Error Modeling and Correction for Reliable Systems Design. Read more...
    Jaan Raik (U. of Talinn, Estonia)
  • 2C.3) Dependable Embedded Systems.
    Jorg Henkel (KIT, DE)

    16.00-17.00 Coffee Break and Poster Session (Foyer)

  • P2.1) On-chip Temperature and Voltage measurement for Field Testing
    Y. Miura (Tokyo Metropolitan Univ.), Y. Sato, Y. Miyake, S. Kajihara (Kyushu Institute of Technology)
  • P2.2) Impact of NBTI on Analog Components
    Z. Lv (Tsinghua University), L. Milor (Georgia Institute of Technology), S. Yang (Tsinghua University)
  • P2.3) Through-Silicon-Via Resistive-Open Defect Analysis
    C. Metzler, A. Todri, A. Bosio, L. Dilillo, P. Girard, A. Virazel (LIRMM)
  • P2.4) Testing of Digitally Assisted Adaptive Analog / RF Systems Using Tuning Knob - Performance Space Estimation
    A. Banerjee, S.K. Devarakond, S. Sen, D. Banerjee, A. Chatterjee (Georgia Institute of Technology)
  • P2.5) On Chip Test Comparison for Secure ICs
    J. Da Rolt, G. Di Natale, M.-L. Flottes, B. Rouzeyre (LIRMM)

    17.00-18.30 Sessions 3

    Session 3A: MPSoCs test (Ravel A)

    Moderator: Bart Vermeulen (NXP, NL)

  • 3A.1) Characterization and Handling of Low-Cost Micro-Architectural Signatures in MPSoCs
    A. Krieg, J. Grinschgl, C. Steger, R. Weiss (Graz University of Technology), A. Genser, J. Haid, H. Bock (Infineon Technologies Austria AG)
  • 3A.2) Reducing Wearout in Embedded Processors using Proactive Fine-Grained Dynamic Runtime Adaptation
    F. Oboril, M. Tahoori (Karlsruhe Institute of Technology)
  • 3A.3) An MPSoCs demonstrator for fault injection and fault handling in an IEEE P1687 environment
    K. Petersen (HDC AB), D. Nikolov, U. Ingelsson, E. Larsson (Linkoping University), G. Carlsson (Ericsson)

    Session 3B: PANEL 1
    VLSI Test Technology: Why is the field not sexy enough? (Verdi A)

    Organizers: Said Hamdioui (TU Delft, The Netherlands), Rob Aitken (ARM, USA)
    Moderators: Said Hamdioui (TU Delft, The Netherlands), Rob Aitken (ARM, USA)
  • Bram Kruseman (NXP, The Netherlands)
  • Piet Engelke (Infineon, Germany)
  • Yervant Zorian (Synopsys, USA)
  • Bob Madge (Global Foundries)
  • Hans-Joachim Wunderlich (Uni. Stuttgart, Germany)
  • Subhasish Mitra (Stanford Uni, USA)
  • Zebo Peng (Linkoping Uni, Sweden)
  • Xiaowei Li (CAS, China)

    Session 3C (vendor): Test and reliability at design time (1) (Berlioz AB)

    Moderator: Abhijit Chaterjee (Georgia Tech University, USA)

  • 3C.1) RTL Analysis for Deep Submicron Test (SpyGlass DFT, DSM and MBIST)
    J. P. Binois (Atrenta Design)
  • 3C.2) Addressing Test Challenges in Advanced Technology Nodes
    S. Talluto, Y. Zorian (Synopsys)
  • 3C.3) From robust designs towards resilient products: an electrical ageing perspective
    V. Huard (STMicroelectronics)

    18.30-19.30 PhD Forum (Ravel A)

    Wednesday, May 30

    8.30-9.15 Keynote (Salle de l'Europe)

    Keynote: 3D Chip Stacking: The Sky Is The Limit

    Erik Jan Marinissen (IMEC,BE)


    9.15-10.45 Sessions 4

    Session 4A: Advanced DFT (Ravel A)

    Moderator: Erik Larson (Lund University, SE)

  • 4A.1) OBT for settling error test of sampled-data systems using signal-dependent clocking
    M. Barragan, G. Leger (IMSE-CNM), J. Huertas (Universidad De Sevilla)
  • 4A.2) On-Chip Delay Measurement Circuit
    A. Jain, A. Veggetti, D. Crippa, P. Rolandi (STMircroelectronics)
  • 4A.3) A Low-Cost DFT Architecture for 3D-SIC Tesing Applications
    C.A. Chen, Y.W. Chen, M.H. Wu, C.L. Hsu, K.L. Luo, L.C. Cheng, W.C. Wu (Industrial Technology Research Institute)

    Session 4B: Advancement in Functional Test Generation and Fault Simulation (Rotonde de l'Europe)

    Moderator: Jaan Raijk (U. Tallin, EE)

  • 4B.1) On the Detection of Path Delay Faults by Functional Broadside Tests
    I. Pomeranz (Purdue University)
  • 4B.2) Functional Test Generation for Hard to Detect Stuck-At Faults using RTL Model Checking
    M. Prabhu, J. Abraham (University of Texas)
  • 4B.3) Exact Stuck-at Fault Classification in Presence of Unknows
    S. Hillebrecht (University of Freiburg), M. Kochte (University of Stuttgart), B. Becker (University of Freiburg), H.-J. Wunderlich (Universitat Stuttgart)

    Special Session 4C: Projects DIANA and MEDIAN (Berlioz AB)

    Moderator: C. Bolchini (Politecnico di Milano, IT)

  • 4C.1) Integrated Diagnostics for the Analysis of Electronic Failures in Vehicles: Project DIANA. Read more...
    Piet Engelke (Infineon, DE)
  • 4C.2) Introducing MEDIAN: a new COST Action on manufacturable and dependable multicore architectures at nanoscale. Read more...
    Marco Ottavi (University of Rome "Tor Vergata", Italy)

    10.45-11.00 Coffee Break (Foyer)

    11.00-12.30 Sessions 5

    Session 5A: SoC testing and self-repair (Ravel A)

    Moderator: Paolo Prinetto (Politecnico di Torino, IT)

  • 5A.1) Memory Reliability Improvements based on Maximized Error-Correcting Codes
    V. Gherman, S. Evain, Y. Bonhomme (CEA)
  • 5A.2) Time-Division Multiplexing for Testing SoCs with DVS and Multiple Voltage Islands
    C. Kavousianos (University of Ioannina), K. Chakrabarty (Duke University), A. Jain, R. Parekhji (Texas Instruments)
  • 5A.3) Combining Dynamic Slicing and Mutation Operators for ESL Correction
    J. Raik, U. Repinski, H. Hantson, M. Jenihhin (Tallinn University of Technology), G. Di Guglielmo, G. Pravadelli, F. Fummi (Universita di Verona)

    Session 5B: Adaptive testing (Rotonde de l'Europe)

    Moderator: Salvador Mir (TIMA Laboratory, FR)

  • 5B.1) Multi-Voltage Aware Resistive Open Fault Modeling
    M.T. Mohammadat (Universiti Teknologi Petronas), N. Basheer Zain Ali (University of Southampton), F. Hussin (Universiti Teknologi Petronas)
  • 5B.2) Indirect Method for Random Jitter Measurement on SoC using Critical Path Characterization
    J.W. Lee, J. Chun (Intel Corporation), J. Abraham (University of Texas)
  • 5B.3) Adaptive Testing of Chips With Varying Distributions of Unknown Response Bits
    O. Sinanoglu (New York University - Abu Dhabi), C. Holenarasipur Suresh (NYU-Poly), S. Ozev (Arizona State University)

    Session 5C (vendor): Test and reliability at design time (2) (Berlioz AB)

    Moderator: Urban Ingelsson (EIS by Semcon, SE)

  • 5C.1) Parallel MBIST and the ARM MBIST interface
    T. McLaurin (ARM)
  • 5C.2) DFT verification for non DFT experts
    C. AKTOUF (DeFacTo)
  • 5C.3) Industrial Challenges in Designing Reliable Systems
    A. Evans, S.-J. Wen, M. Warriner (CISCO)

    12.30-14.00 Lunch

    14.00-15.00 Sessions 6: Embedded Tutorials

    Session 6A: Embedded tutorial 1 (Verdi AB)

    Moderator: Goerschwin Fey (University of Bremen, D)

  • 6A) Adaptive Testing: Conquering Process Variations
    Presenters: Sule Ozev (ASU, USA), Peter Maxwell (Aptina, USA), Ozgur Sinanoglu (NYU AD, EAU)

    Session 6B: Embedded tutorial 2 (Rotonde de l'Europe)

    Moderator: Luigi Dilillo (LIRMM, FR)

  • 6B) Introduction to the Defect-Oriented Cell-Aware Test Methodology for significant reduction of DPPM rates
    Presenter: Friedrich Hapke (Mentor Graphics, DE)

    15.30 Social Event


    Thursday, May 31

    9.00-10.00 Sessions 7

    Session 7A: Built-in Self Test (Rotonde de l'Europe)

    Moderator: Gert Jervan (Tallin U of Technology, EE)

  • 7A.1) Toggle-Masking Scheme For X-Filtering
    O. Sinanoglu (New York University - Abu Dhabi), A. Ramdas (NYU-Poly)
  • 7A.2) Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test
    A. Cook (University of Stuttgart), S. Hellebrand (University of Paderborn), H.-J. Wunderlich (Universitat Stuttgart)

    Session 7B: SAT-based Test Pattern Generation (Ravel A)

    Moderator: Zebo Peng (Linkoping University, SE)

  • 7B.1) Multi-Conditional SAT-ATPG for Power-Droop Testing
    A. Czutro, M. Sauer (University of Freiburg), I. Polian (University of Passau), B. Becker (University of Freiburg)
  • 7B.2) On the Quality of Test Vectors for Post-Silicon Characterization
    M. Sauer, A. Czutro, B. Becker (University of Freiburg), I. Polian (University of Passau)

    Session 7C (vendor): Production test (Berlioz AB)

    Moderator: Paolo Bernardi (Politecnico di Torino, IT)

  • 7C.1) T2000 IPS Efficient Test Solution for Integrated Power Devices
    A. Dirscher (Advantest)
  • 7C.2) Near Real-Time Monitoring and Business Intelligence System for Volume Production Test data
    R. Segers, S. Iung, D. De Vries, P. Simon (Qualtera)

    10.00-11.00 Coffee Break, Poster Session, and PhD Awards (Foyer)

  • P3.1) Fault-Tolerant Algebraic Architecture for Radiation-Induced Soft-Errors
    F. Itturriet, R. Ferreira, L. Carro (Universidade Federal do Rio Grande do Sul)
  • P3.2) Online Detection and Recovery of Transient Errors in Front-end Structures of Microprocessors
    M. Tahoori (Karlsruhe Institute of Technology), S. Shazli (Northeastern University)
  • P3.3) Test tool qualification through fault injection
    Q. Wang, A. Wallin, V. Izosimov, U. Ingelsson (Embedded Intelligent Solutions By Semcon AB), Z. Peng (Linkoeping University)
  • P3.4) A Software-Based Self-Test Methodology for On-Line Testing of Data TLBs
    G. Theodorou, S. Chatzopoulos, N. Kranitis, A. Paschalis, D. Gizopoulos (University of Athens)
  • P3.5) Embedded Synthetic Instruments for Board-Level Testing
    I. Aleksejev, A. Jutman, S. Devadze (Tallinn University of Technology)

    11.00-12.30 Sessions 8: Panels

    Session 8A: Panel 2
    The impact of functional safety standards in the design and test of reliable and available integrated circuits. (Rotonde de l'Europe)

    Organizer: Riccardo Mariani (YOGITECH SpA, Italy)
  • Pascal Chaumette (BWI Group)
  • Frank Reichenbach (ABB Corporate Research Norway)
  • Petr Sladecek (STMicroelectronics)
  • Pete Harrod (ARM)
  • Victor Reyes (Synopsys)
  • Hari Pendurty (Texas Instruments)

    Session 8B: Panel 3
    Re-using Chip Level DFT at Board Level (Ravel A)

    Organizers: Xinli Gu (Huawei), Krishnendu Chakrabarty (Duke University), Erik Larsson (Lund University)
    Moderator: Artur Jutman (Testonica)
  • Jeff Rearick (AMD)
  • Bill Eklow (Cisco)
  • Martin Keim (Mentor Graphics)
  • Jun Qian (AMD)

    12.30-14.00 Lunch

    14.00-15.00 Session 9

    Session 9A: System and Board-level testing (Rotonde de l'Europe)

    Moderator: Matteo Sonza Reorda (Politecnico di Torino, IT)

  • 9A.1) Efficient System-Level Aging Prediction
    N. Hatami (Politecnico di Torino), R. Baranowski (University of Stuttgart), P. Prinetto (Politecnico di Torino), H.-J. Wunderlich (Universitat Stuttgart)
  • 9A.2) Diagnostic System Based on Support-Vector Machines for Board-level Functional Diagnosis
    Z. Zhang, X. Gu, Y. Xie, Z. Wang, Z. Wang (Huawei Technologies), K. Chakrabarty (Duke University)

    15.00-15.30 Closing (Rotonde de l'Europe)

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