IEEE International Workshop on Processor
Verification, Test and Debug (IWPVTD'11)
- The deadline for submissions has been
extended to 23rd March.
- Updated info on
this
link
 .
Modern computer system and systems-on-chip are
built around high speed processors in order to meet consumer demand for
performance and rich functionality. The increasing size and complexity of these
designs, along with time-to-market pressure, has put enormous pressure on
verification to ensure bug-free design. While eliminating all bugs remains an
unfulfillable dream, catching more problems earlier in the design cycle is top
priority. Moreover, design complexity means that some bugs may only be
discovered during post-silicon debug, mandating inclusion of built-in debug
features to simplify the process.
Aggressive processor design methodologies in
nanometer technologies include high speed clocks, power control, environmental
awareness, and complex memory interfaces. Test and verification are needed for
all of these. In addition many reliability challenges, manufacturing
variations, soft errors, wearout, etc. will need to be addressed by innovative
new design and test methodologies if device scaling is to continue on track as
per Moore's Law to 10nm and beyond. This event will bring together the
processor design, verification, and test engineers and researchers to develop a
holistic approach to develop verification, test and debug solutions.
The key objective of this workshop, planned to
be held in conjunction with the European Test Symposium, is to provide an
informal forum for vigorous creative discussion and debate of this area. The
aim is to encourage the presentation and discussion of innovative ideas that
may not yet have been fully developed for presentation at reviewed conferences
to address these challenges. Additionally, the workshop invites embedded talks
and tutorials on cutting edge topics related to processor test, verification,
debug and reliability.
Download call for papers (pdf). |
